Digital data communication system

ABSTRACT

A digital data transmission system comprising a plurality of interconnected switching units, each such unit having connected thereto at least one transmission loop, and each such loop having at least one digital device attached thereto. The system provides controllable buffering of digital data thereby allowing digital devices having different data transfer speeds and storage capabilities to communicate asynchronously. The system allocates communication resources upon request but only creates actual communication paths when the requesting device is transmitting data. Thus system resources need not remain committed between bursts of data.

BACKGROUND OF THE INVENTION

1. Field of the Invention

This invention relates to digital transmission systems and, moreparticularly, to digital transmission by asynchronous message switchingon a common time-divided transmission loop.

2. Description of the Prior Art

It is often desirable to exchange digital information between digitalmachines. If such machines are separated by any significant geographicdistance, it has heretofore been necessary to either purchase or lease adedicated transmission facility between such machines, or to arrange atemporary connection between such machines by means of common carrier,switched transmission facilities. Since it is the nature of digitalmachines to require large amounts of digital channel capacity, but onlyfor brief periods and only occasionally, the heretofore availablefacilities described above have proven very inefficient for this use.Dedicated transmission facilities, for example, remain unused the vastmajority of the time. Switched, common carrier facilities tend to berestricted in bandwidth to voice frequencies and hence are notimmediately adaptable to high speed digital transmission.

A further problem with switched facilities is the fact that it oftentakes more time to set up the transmission path than is required for theentire transmission of data. The telephone network requires real timetransmission in the sense that signals must be delivered substantiallyat the same time they are generated. It therefore is standard procedureto set up the communication path in its entirety before any signals aretransmitted. As a result, centralized switching has been used in thetelephone plant. Digital transmission of data, on the other hand, neednot be done in real time and hence it is wasteful to set up an entireconnection prior to transmission. These facts tend to make presentlyavailable interconnection facilities uneconomical for intermachinedigital communications.

It is therefore an object of the present invention to provide improveddigital transmission between digital machines.

It is another object of the present invention to allow digital machineshaving widely varying data handling capabilities to communicateefficiently and ecomonically.

It is a further object of this invention to provide a system whichallows a digital machine to communicate with a plurality of otherdigital machines without the need for reprogramming that machine whenthe number or capabilities of machines in the system is changed.

It is a still further object of this invention to provide an algorithmwhich takes advantage of the inherent characteristics of digitalmachines to provide a more efficient method of using transmissionresources.

SUMMARY OF THE INVENTION

These objects are achieved in accordance with this invention by a systemof interconnected transmission loops. The system includes a plurality ofinterconnected switching units which comprise general-purposeprogrammable digital computers. Each switching unit has at least onetransmission loop connected to it. Each loop includes at least one loopaccess module and each module has attached to it a terminal interfaceunit to which a digital device is connected.

Each switching unit controls the data transmission to and from thedigital devices that are attached to its transmission loops. Eachdigital device may be allocated up to 256 different channels, one ofwhich is used solely for signalling between the digital device and itsassociated switching unit. The switching unit controls the allocationand actual implementation of the remaining 255 of these channels by aprocess that may be termed "virtual allocation."

When a request to make a connection is received, the switching unitdetermines and stores the characteristics of the transmission pathrequired to honor the request. No actual transmission paths are set upat this time and no actual system resources are assigned except for theamount of the switching unit memory used to store the transmission pathcharacteristics. The transmission path is actually set up only when thedigital device begins to transmit data. The data flow is then controlledin accordance with the previously determined characteristics by a novelalgorithm embodying a request-acknowledge process. A transmission pathis actually maintained only as long as data is being transmitted. Thetransmission path otherwise remains only virtually allocated. Since itis characteristic of digital devices to transmit data in bursts withpauses between bursts, this method of controlling the system eliminatesidle transmission paths. This more efficient use of transmissionresources allows a greater volume of data to be handled.

The loop access modules serve to keep data flowing around thetransmission loops and to provide an interface between the loops and theterminal interface units. The terminal interface units transfer data ona full duplex basis between their associated digital device and the restof the system. Each terminal interface unit includes a smallprogrammable digital computer which interacts with the computer in theswitching unit to control the signaling between the switching unit andthe associated digital device and which serves to control the transferof data to and from the digital device.

The algorithm that governs the transmission of data in the systemcomprises two program portions, one stored in and executed by theswitching unit, the other stored in and executed by the computercontained in the terminal interface unit. This algorithm utilizes thecharacteristics of the requested data transfer to determine the systemresources that will be required. During the actual data transmission,the algorithm provides for the buffering that is required to allow therequesting digital device to transmit data to the receiving digitaldevice. Thus the algorithm serves to match the data transmissioncharacteristics of the transmitting digital device to the data receptioncharacteristics of the receiving digital device.

BRIEF DESCRIPTION OF THE DRAWING

FIG. 1A is a general block diagram of a digital transmission system inaccordance with this invention;

FIG. 1B illustrates the manner in which data and signalling informationis transmitted in the system of FIG. 1A;

2A is a more detailed diagram of the switching unit shown in FIG. 1A;

FIG. 2B is a more detailed diagram of a part of the transmission systemshown in FIG. 1A;

FIG. 3A illustrates the format of the signals appearing on thetransmission lines and transmission loops shown in FIG. 1A;

FIG. 3B is an expanded view of a portion of FIG. 3A;

FIG. 4A shows the manner in which the line format shown in FIG. 3A isutilized in this invention;

FIG. 4B is an expanded view of a portion of FIG. 4A;

FIG. 4C is a further expanded view of a portion of FIG. 4A;

FIGS. 5A and 5B are a logic diagram of the loop transmit buffer shown inFIG. 2B;

FIG. 5C is a logic diagram of the rising edge trigger circuit used inthe loop transmit buffer shown in FIG. 5A;

FIGS. 5D and 5E are a logic diagram of the loop receive buffer shown inFIG. 2B;

FIG. 5F is a logic diagram of the falling edge trigger circuit used inthe loop receive buffer shown in FIG. 5D;

FIGS. 6A through 6H are a logic diagram of the data multiplexer shown inFIG. 2B;

FIG. 6I shows the interconnection of FIGS. 6A through 6H;

FIG. 7A is a block diagram of the terminal buffer shown in FIG. 2B;

FIG. 7B is a timing diagram useful in understanding the operation of theterminal buffer shown in FIG. 7A;

FIG. 7C is a more detailed diagram of the data receive buffer shown inFIG. 7A;

FIG. 7D is a more detailed diagram of the data transmit buffer shown inFIG. 7A;

FIG. 7E is a more detailed diagram of the channel select circuit shownin FIG. 7A;

FIG. 7F is a more detailed diagram of the channel break circuit shown inFIG. 7A;

FIG. 8 is a representation of an instruction word used by the interfacecomputer shown in FIG. 2B;

FIG. 9A is a block diagram of the interface computer shown in FIG. 2B;

FIG. 9B is a timing diagram useful in understanding the operation of theinterface computer shown in FIG. 9A;

FIGS. 9C, 9D, and 9E are a logic diagram of the interface computer shownin FIG. 9A;

FIG. 9F shows the interconnection of FIGS. 9C, 9D, and 9E;

FIG. 9G is a logic diagram of a clock circuit used in the interfacecomputer shown in FIG. 9A;

FIG. 10A is a functional diagram that illustrates the data and signaltransfer between the digital device, terminal interface unit, andswitching unit shown in FIG. 1A;

FIG. 10B is a functional diagram that illustrates the data and signaltransfer between the switching units shown in FIG. 1A;

FIGS. 11A, 11B, and 11C show the formats of the data and signals thatare transmitted in the system of FIG. 1A;

FIG. 12 is a flow chart of the initialization instructions executed bythe interface computer shown in FIG. 2B;

FIGS. 13A and 13B are a flow chart of the data output routine executedby the interface computer shown in FIG. 2B;

14A and 14B are a flow chart of the data input routine executed by theinterface computer shown in FIG. 2B;

FIG. 15 is a flow chart of the signal output routine executed by theinterface computer shown in FIG. 2B;

FIGS. 16A and 16B are a flow chart of the signal input routine executedby the interface computer shown in FIG. 2B;

FIGS. 17A through 17L show the data structures used by the controlcomputer shown in FIG. 2B;

FIGS. 18A, 18B, 18C and 18D are a flow chart of the call managementroutine executed by the control computer shown in FIG. 2B;

FIG. 19A is a flow chart of the decode route routine executed by thecontrol computer shown in FIG. 2B;

FIG. 19B is a flow chart of the trace route routine executed by thecontrol computer shown in FIG. 2B;

FIG. 19C is a flow chart of the remove subchannel routine executed bythe control computer shown in FIG. 2B;

FIGS. 19D and 19E are a flow chart of the create subchannel routineexecuted by the control computer shown in FIG. 2B;

FIG. 19F is a flow chart of the find queue routine executed by thecontrol computer shown in FIG. 2B;

FIGS. 20A-20D are a flow chart of the data input routine executed by thecontrol computer shown in FIG. 2B;

FIGS. 21A and 21B are a flow chart of the data output routine executedby the control computer shown in FIG. 2B;

FIGS. 22A through 22F are a flow chart of the signal input routineexecuted by the control computer shown in FIG. 2B;

FIGS. 23A and 23B are a flow chart of the signal output routine executedby the control computer shown in FIG. 2B;

FIGS. 24A and 24B are a flow chart of the timeout routine executed bythe control computer shown in FIG. 2B;

FIG. 25A is a flow chart of the S.BURST.IN subroutine executed by thecontrol computer shown in FIG. 2B;

FIG. 25B is a flow chart of the E.BURST.IN subroutine executed by thecontrol computer shown in FIG. 2B;

FIG. 25C is a flow chart of the S.BUNDLE.IN subroutine executed by thecontrol computer shown in FIG. 2B;

FIGS. 25D and 25E are a flow chart of the S.BURST.OUT subroutineexecuted by the control computer shown in FIG. 2B;

FIG. 25F is a flow chart of the E.BURST.OUT subroutine executed by thecontrol computer shown in FIG. 2B;

FIG. 25G is a flow chart of the S.BUNDLE.OUT subroutine executed by thecontrol computer shown in FIG. 2B;

FIG. 25H is a flow chart of the REQSIG subroutine executed by thecontrol computer shown in FIG. 2B;

FIG. 25I is a flow chart of the REQOUT subroutine executed by thecontrol computer shown in FIG. 2B;

FIG. 25J is a flow chart of the ASSIGN.SPACE subroutine executed by thecontrol computer shown in FIG. 2B;

FIG. 25K is a flow chart of the RELEASE.SPACE subroutine executed by thecontrol computer shown in FIG. 2B;

FIG. 25L is a flow chart of the ASSIGN.TRUNK subroutine executed by thecontrol computer shown in FIG. 2B;

FIG. 25M is a flow chart of the RELEASE.TRUNK subroutine executed by thecontrol computer shown in FIG. 2B; and

FIG. 25N is a flow chart of the RETREAT subroutine executed by thecontrol computer shown in FIG. 2B.

DETAILED DESCRIPTION

Before proceeding to a detailed description of the drawings, it shouldbe noted that all of the circuits described herein may be realized, inthe illustrative embodiment, by using integrated circuits. Suitablecircuits can be found, for example, in "The Integrated Circuit Catalog,"first edition, Catalog CC401, published by Texas Instruments, Inc. and,alternatively, in "The Microelectronics Data Book," second edition, byMotorola Semiconductor Products, Inc., dated December, 1969.

Referring more particularly to FIG. 1A, there is shown a graphicalrepresentation of a data transmission system in accordance with thepresent invention. The system comprises a plurality of switching units10 which are interconnected by means of transmission lines 12. Eachswitching unit 10 has attached thereto at least one transmission loop14. Each such transmission loop 14 is connected to at least one loopaccess module 16. Loop access module 16 serves to steer data around loop14 and to take data from the loop and place data on the loop in themanner to be described in greater detail hereinbelow. Each loop accessmodule 16 is connected to a terminal interface unit 17 which provides aninterface between an attached digital device 18 and the remainder of thesystem. Data transmission in the system is primarily controlled by theinteraction of terminal interface unit 17 and switching unit 10.

This interaction is shown schematically in FIG. 1B. FIG. 1B illustratesa full-duplex transmission path in which one terminal interface unit 19of the type shown in FIG. 1A transmits data to another terminalinterface unit 23 which receives it. The receiving terminal interfaceunit 23 responds by sending either data or signals or both back to thetransmitting terminal interface unit 19. Since the transmission path isfull-duplex, these actions can occur simultaneously.

While it is possible for two terminal interface units 17 (FIG. 1A) onthe same transmission loop 14 to communicate, a typical communicationwill, as shown in FIG. 1B, involve more than one switching unit. Thedetailed system algorithm by which this communication takes place isdescribed hereinbelow following the detailed descriptions of theapparatus shown in FIG. 1A. However, a consideration of the followingbrief description of the process of communication in the system of FIG.1A will make the apparatus description more readily understandable.

The digital transmission system of FIG. 1A provides each digital device18 that uses the system with the capability of selecting up to 256 otherdevices in the system to which it can transmit data or from which it canreceive data. Each such selection comprises a "channel" which is usedherein to mean a previously selected route. Thus it is as if eachdigital device had attached to it 256 full-duplex channels each of whichit could use on a one-at-a-time basis to send or receive data. Althougheach device has only 256 channels, the destinations of these channelscan be changed by the device as desired. One of these channels isreserved for communication with the switching unit that controls thetransmission loop to which the particular device is attached. Thischannel, termed the "control channel," is used by the terminal interfaceunit associated with the digital device to set up a data transmissionpath by providing the most immediately associated switching unit withthe full address of the intended destination of the data appearing oneach of the remaining 255 channels. The control channel is also used bythe switching unit to command the digital device to pick the channel onwhich it wishes to receive data being sent by another digital device.The switching unit maintains a list showing the correspondence betweenthe absolute addresses and the 256 channels of each of the digitaldevices connected to it. Thus for each transmission or reception, adigital device need only handle an eight bit address. FIG. 1Billustrates a single full-duplex channel between a transmitting terminalunit 19 and a receiving terminal unit 23. Terminal interface units 19and 23 and the switching units 20, 21, and 22 are shown as comprisingcomponents labeled with subscripted α's and β's. The label "α" isassociated with the transmission of data while the label "β" isassociated with the reception of data. The connection between aparticular α and the β to which it transmits is termed a "link." Thesubscript "T" is associated with that half of the full-duplex path,which is termed a "subchannel" and shown in FIG. 1B as path 15, thattransmits data from the transmitting terminal interface unit 19 to thereceiving terminal interface unit 23. The subscript "R" is associatedwith the other subchannel of the full-duplex path.

The α and β "components" referred to above and shown in FIG. 1B refernot to apparatus but to stored processes and parameters which serve tocontrol the transmission and reception of data between the terminalinterface units and the switching units. The α processes use the αparameters to control transmission of data while the β processes use theβ parameters to control reception of data. The exact manner in whichthese processes provide the desired data communication will be discussedin greater detail below. In general, a terminal interface unit will onlyhave a single set of α parameters and a single set of β parameters, bothsets of which are uniquely determined by the characteristics of theparticular associated digital device. Hence the α and β parameters of aterminal interface unit remain the same for each of the 256 channels onwhich it can communicate.

This is not true, however, for the switching units. Each switching unitwill, at any instant, be communicating on only a particular one of the256 full-duplex channels of a specified terminal interface unit. Eachhalf of this channel has an associated α-β pair which need notcorrespond to the α-β pair on the other half of the channel. In theexample shown in FIG. 1B, α_(T1) represents the transmittingcharacteristics of transmitting terminal interface unit 19, while β_(Rn)represents the receiving characteristics of that unit. Switching unit 20receives data on link 24 from terminal interface unit 19 in accordancewith the parameters β_(T1) and retransmits the data to switching unit 21on link 25 in accordance with parameters α_(T2). Similarly, switchingunit 20 receives data sent by receiving terminal interface unit 23 fromswitching unit 21 on link 28 in accordance with parameters β_(R)(n-1)and retransmit it to transmitting terminal interface unit 19 on link 29in accordance with parameters α_(Rn).

Each switching unit has two α-β pairs for each full-duplex channel whichis routed through it. Thus switching unit 22 may have, for example, notonly the two α-β pairs shown in FIG. 1B, but also other such pairsallocated for other channels from other terminal interface unitsassociated with both switching unit 20 and switching unit 21. Theallocation of such pairs in various switching units is termed "virtualallocation" since all that need be done is to store the correct α-βpairs. Thus many channels may be virtually allocated at any one time. Aparticular channel may be actually activated by directing the pertinentswitching units to begin receiving and retransmitting data on a halfduplex basis in accordance with that particular channel's α-βappropriate pair.

Continuing then with the description of the apparatus of FIG. 1A, FIG.2A is seen to be a more detailed description of a single switching unit10. Each switching unit 10 comprises a single control computer 30 whichcommunicates with a plurality of line terminating units 31. One lineterminating unit 31 is required for each transmission loop 14 and eachtransmission line 12 that is connected to switching unit 10. These unitsserve to output data from control computer 30 onto transmission loops 14and transmission lines 12. Transmission lines 12 as well as transmissionloops 14 are of the type suitable for synchronous, digital, fixed-frametransmission. In the following discussion of the exemplary embodiment ofthis invention, it will be assumed that transmission lines 12 andtransmission loops 14 comprise standard T1 carrier lines of the typewell known in the prior art.

FIG. 2B is a more detailed diagram of the apparatus required to controla single transmission loop to which is connected a single loop accessmodule 16. Since each line terminating unit 31 operates in the samemanner irrespective of whether it is connected to a transmission line 12or a transmission loop 14, a detailed description of the apparatus shownin FIG. 2B will suffice to explain the operation of the system shown inFIG. 1A.

Turning then to control computer 30 shown in FIG. 2B, it is this devicethat performs the aforementioned processes of virtual allocation andactual activation of channels that is required to enable terminalinterface unit 17 to communicate with other terminal interface units inthe system. Control computer 30 may be any of the many commerciallyavailable general-purpose digital-computers. The computer chosen for anyparticular implementation will be determined by the size of the systemthat is desired. In the following discussion, computer 30 is assumed tobe a TEMPO 1 computer which is manufactured by TEMPO Computers,Incorporated, a division of General Telephone and Electronics,Incorporated.

Control computer 30 is connected to loop transmit buffer 34 of lineterminating unit 31 by means of lines 32. Since the TEMPO 1 computer hasa sixteen-bit output, lines 32 shown in FIG. 2B comprise 16 separatewires which interconnect the output register of the TEMPO 1 computer andthe loop transmit buffer 34. Loop transmit buffer 34 temporarily storesthe sixteen-bit words output by the control computer 30. After bufferingthis data, the loop transmit buffer 34 outputs it to the bytedisassembler 40. Each such output comprises a ten-bit word, eight bitsof data from the control computer 30 and two bits of control informationwhich are supplied by the circuitry of the loop transmit buffer 34 inthe manner which is described in conjunction with FIGS. 5A and 5B.

These twelve-bit words are transferred from loop transmit buffer 34 tobyte disassembler 40 of line terminating unit 31 by means of lines 38which comprise twelve wires, one for each bit. Byte disassembler 40serves to transform the output of loop transmit buffer 34 into serialdata for transfer to terminal matching unit 42 over line 44.

Terminal matching unit 42 of line terminating unit 31 supplies theinterface that connects the input and output of control computer 30 tothe transmission loop 14 or, alternatively, to a transmission line 12for those line terminating units 31 that are connected to transmissionlines 12. This terminal matching unit comprises standard T1 equipmentwhich can be commercially obtained from the Vicom division of the VidarCorporation as the Vicom 2020 Terminal Matching Unit. Terminal matchingunit 42 is connected to office repeater 50 by means of lines 46 and 48.Lines 46 comprise a pair of wires which allow data to be transmittedfrom control computer 30 to transmission loop 14 and lines 48 comprise apair of wires which allow data to be transmitted from transmission loop14 to control computer 30.

Office repeater 50 serves to provide power for the T1 line comprisingtransmission loop 14. This unit is also commercially available under thename of Vicom 2010 Office Repeater.

As can be seen in FIG. 2B, data flows out of office repeater 50 ontotransmission loop 14 and is transferred to line repeater 52 which iscontained in loop access module 16. Line repeater 52 serves toretransmit data received on transmission loop 14 from office repeater 50and also serves as the means by which loop access module 16 takes datafrom line 14 and places data onto loop 14. Line repeater 52 is also apiece of commercial T1 equipment which is obtainable under the name ofthe Vicom 1550-04 Self-Equalizing Line Repeater. Line repeater 52 isline powered and serves to automatically adjust for variations in thelength of cable between adjacent repeaters subject to a rangelimitation. In those implementations in which loop access modules arevery close together and hence out of the compensation range of therepeaters, 15 decibel artificial cable networks may be inserted betweenrepeaters in a manner which will be apparent to those of ordinary skillin the art.

In order to insure proper operation of the system if power should failat a particular loop access module, each loop access module 16 isprovided with a protection relay 54. Protection relay 54 has transfercontacts which when unenergized connect lines 78 and 80, and whenenergized connect lines 79 and 80. Thus if a signal is not supplied toprotection relay 54 on line 77 by power monitors 76, the protectionrelay will short-circuit loop access module 16 and simply allow data tobe retransmitted on transmission loop 14 by line repeater 52.

Power monitor 76 is a triggerable one-shot multivibrator and will hencesupply an output signal as long as it is supplied with power fromterminal interface unit 17 and is also continuously triggered by ANDgate 73. AND gate 73 has two inputs, one from interface computer 62which is periodically supplied if interface computer 62 is functioningproperly, and one from data multiplexer 58 through inverter 74. Thesignal supplied by data multiplexer 58 indicates that a framing errorwas detected in the data input on lines 71. Inverter 74 thus inhibitsAND gate 73 when an error signal is supplied by data multiplexer 58 online 75.

Matching unit 56 of loop access module 16 shown in FIG. 2B serves thesame function as terminal matching unit 42. Indeed, matching unit 56 mayalso comprise a Vicom 2020 Terminal Matching Unit.

Data multiplexer 58 of terminal interface unit 17 shown in FIG. 2Bserves to receive data from matching unit 56 of loop access module 16 onlines 71, and to transfer data to matching unit 56 on lines 72. Datamultiplexer 58, shown in greater detail in FIGS. 6A-6I, serves toassemble the serial data coming from matching unit 56 into eight-bitwords for transmission to terminal buffer 60, and also serves todisassemble eight-bit words from terminal buffer 60 into serial data tobe transferred back to matching unit 56.

Terminal buffer, 60, which is explained in greater detail in conjunctionwith FIGS. 7A-7F, serves to buffer data going to and coming from digitaldevice 18. This buffer serves to isolate digital device 18 from thesynchronous speed of transmission loop 14.

The control of terminal interface unit 17 is provided by the interfacecomputer 62. Interface computer 62, which is explained in greater detailin conjunction with FIGS. 9A-9F, is a digital computer which has alimited instruction repertoire. This instruction repertoire is, however,sufficiently flexible to allow programming the interface computer 62 todo the variety of tasks which are of critical importance in theimplementation of the aforementioned transmission algorithm. In thisillustrative embodiment a specially designed digital computer isdisclosed; however, the functions performed by interface computer 62could alternatively be implemented by using a commercial digitalcomputer as will become apparent to those of ordinary skill in the artby the further discussion of interface computer 62.

Serial data emerging from line repeater 52 of loop access module 16returns to control computer 30 by way of the office repeater 50 andterminal matching unit 42. The data is transferred serially fromterminal matching unit 42 by line 6200 to byte assembler 64. Byteassembler 64 performs the converse of the operation performed by bytedisassembler 40; that is, it assembles the serial data from terminalmatching unit 42 into eight-bit bytes for transmission to loop receivebuffer 66 on lines 68.

Loop receive buffer 66 operates in a manner analogous to loop transmitbuffer 34 and is explained more fully in conjunction with FIGS. 5D and5E.

Before proceeding to the more detailed diagrams of the apparatus shownin FIG. 2B, it will be advantageous to consider first the data format ofthe system as shown in FIGS. 3A and 3B.

The format shown in FIG. 3A is seen to be the standard T1 line format.The bit sequence appearing on the T1 line is divided into standardframes each comprising a framing bit followed by 192 time slots. Theframing bit alternates between a "1" and a "0" on successive frames. Theconcatenation of two successive standard frames will be termed herein a"master frame" and is understood to always begin with a frame whoseframing bit is a 1.

The 192 time slots of a standard frame are seen in the expanded view inFIG. 3B to be further subdivided into 24 subgroups of eight slots each.These slots in each subgroup are labeled "1" through "8," respectively.As shown, a 1 line bit occupies fifty percent of the time slot allottedto it, thereby resulting in a fifty percent duty cycle pulse train. Asis well known in the prior art, it is necessary when using a T1 line toinsure that there are enough 1 bits on the line to keep the systemclocks operational. To accomplish this, a 1 bit, which is commonlytermed a "keep-alive bit," is inserted into the sixth slot of everyeight-slot subgroup.

When the serial data on the transmission line is used in the system,such as by byte assembler 64 and data multiplexer 58 shown in FIG. 2B,the framing and keep-alive bits are ignored in the formation of thebyte. Excluding these two types of bits, it can thus be seen that 42eight-bit bytes are formed in a master frame.

The line format provided by the standard T1 line is utilized by theapparatus of the illustrative embodiment of this invention in the mannershown in FIGS. 4A, 4B, and 4C. Both the network signaling and thetransmission of system data are multiplexed onto the same line in thesame manner. Of the 42 bytes that exist in a master frame, the firstfour bytes shown in FIG. 4B are reserved exclusively for network controlsignaling, and the remaining 38 bytes are reserved for user supplieddata. The first four bytes will be termed hereinafter a "signal packet"and the remaining 38 bytes will be termed a "data packet." As can beseen in FIG. 4B, signal packets and data packets are completelyindependent even though they occur as a pair within a master frame. Thefirst byte of each packet is understood to be reserved for anidentification code or a special code indicating that the packet iscurrently empty. The packet formats are discussed in greater detailhereinbelow in conjunction with FIGS. 11A through 11C.

LOOP TRANSMIT BUFFER

Continuing then with the detailed description of the circuitry shown inFIG. 2B, FIGS. 5A and 5B are seen to comprise a detailed diagram of theloop transmit buffer 34 shown in FIG. 2B. As shown in FIG. 5A, the inputto the loop transmit buffer 34 comprises a sixteen lines 150 fromcontrol computer 30. The output of the loop transmit buffer compriseseight lines 151 which are applied to byte disassembler 40.

Loop transmit buffer 34 buffers data coming from control computer 30 andoutputs it to byte disassembler 40 in the proper sequence at the propertime. This function is accomplished through the control of memory 152shown in FIG. 5B. Memory 152 is a thirty-two word by sixteen-bit storewhich can be formed, for example, of eight integrated circuit memoriessuch as bipolar LSI memory 3101 manufactured by Intel Corporation. Underthe control of the logic circuitry shown in FIGS. 5A and 5B, sixteen-bitwords are read into memory 152 from control computer 30 while, onalternate byte strobe signals issued on line BS from byte disassembler40, eight-bit words are read out of memory 152 on either of the eightlines 154 or the eight lines 155 into eight-bit register 156 from whencethey are clocked out to byte disassembler 40. The manner in which thecontrol logic accomplishes this is as follows.

Clock 186 shown in FIG. 5A provides the basic timing for loop transmitbuffer 34. This clock comprises an astable multivibrator which runs at a5 megahertz rate. The output of clock 186 is applied to flip-flop 158which is a triggered flip-flop; that is, it changes state each time itreceives a pulse from clock 186. Flip-flop 158 serves to divide thepulse train from clock 186 into two pulse trains operating at one-halfthe frequency of clock 186. The Q output of flip-flop 158 is applied toAND gate 159 while the Q output of flip-flop 158 is applied to AND gate160. Additionally, each of these two gates have as their second inputthe output of clock 186. Thus the outputs from AND gates 159 and 160 areseen to be two 2.5 megahertz pulse trains that are 180° out of phase.The pulse train from AND gate 159 is used to read sixteen-bit words fromcontrol computer 30 into memory 152, while the output from AND gate 160is used to read eight-bit bytes from memory 152 to byte disassembler 40.

First consider the reading of sixteen-bit words from control computer 30into memory 152. This process is accomplished on a command-acknowledgebasis. Commands from control computer 30 are transferred on line 163 torising edge trigger 164. This trigger, which is shown in greater detailin FIG. 5C, provides a strobe output to NAND gate 161 upon receipt of acommand from control computer 30 unless an inhibit signal has beenreceived from six-bit comparator 166 in accordance with the discussionhereinbelow. The rising edge trigger circuit 164 also serves, unless itis inhibited, to supply an acknowledge signal to control computer 30 online 165 each time it receives a command.

RISING EDGE TRIGGER CIRCUIT OF THE LOOP TRANSMIT BUFFER

Rising edge trigger circuit 164 is shown in greater detail in FIG. 5C.In the circuit's quiescent state both of D-type flip-flops 189 and 193have a 1 on their Q outputs causing the strobe output to be a 0 and theacknowledge output to be a 1. A strobe pulse is generated in response toa command being applied to the D input of flip-flop 189. When a commandis applied, flip-flop 189 changes to its set state the next time a clockpulse is applied to the clock input of flip-flop 189. Since at the timeflip-flop 189 becomes set flip-flop 193 is still reset, AND gate 194goes to a 1 output, thus beginning the strobe pulse output.

The trailing edge of the clock pulse that sets flip-flop 189 is coupledthrough inverter 192 to the clock input of flip-flop 193. This allowsthe 0 on the Q output of flip-flop 189 to be coupled through NAND gate191 to the D input of flip-flop 193, causing it to change state. Theacknowledge line thus falls, causing the output of AND gate 194 to fall,thereby terminating the strobe pulse output. The circuit remains in thisstate until the command line falls, at which time it returns to itsquiescent state until the command line is again raised.

The generation of the strobe pulse output will be inhibited if a 1 isapplied to the inhibit input. Inverter 190 converts this into a 0 whichprevents NAND gate 191 from responding to the Q output of flip-flop 189.This, in turn, prevents the acknowledge output from going to a 1.

Returning then to FIG. 5A, NAND gate 161 is thus seen to be enabledwhenever the strobe signal from rising edge trigger 164 corresponds withthe output from gate 159. When both these inputs are simultaneouslypresent at gate 161, it generates an output signal to memories 167 and152 and to six-bit counter 168. This output signal causes memories 167and 152 to store the words currently appearing on their inputs.

Memory 167 is a thirty-two-word-by-two-bit memory which serves to storetwo bits of information which are applied to memory 167 by controlcomputer 30 on lines 169 and 170. These two bits comprise statusinformation which is output to byte disassembler 40 at the appropriatetime. The bit appearing on line 169 signifies the type of packetcurrently being transmitted, either a data packet or a signal packet,and the bit on line 170 serves to indicate when byte zero of either asignal packet or a data packet is being transmitted.

Six-bit counter 168 serves to keep track of the address in each ofmemories 167 and 152 which is currently being written into by controlcomputer 30. The same addresses in each of memories 167 and 152 arealways simultaneously addressed. The output from gate 161 incrementssix-bit counter 168 each time a command is received from controlcomputer 30 to store another word into memories 167 and 152. This servesto provide the correct address for the storage that follows the nextcommand from control computer 30.

Turning then to the apparatus which transfers eight-bit bytes of thewords stored in memories 152 and 167 to byte disassembler 40, thisapparatus is seen to be under the control of ten-bit shift register 171.Shift register 171 receives both of its inuts from byte disassembler 40.One of these inputs, the D₃₆ input, comprises a signal that falls to a 0ech time byte disassembler 40 requests the thirty-sixth byte of athirty-eight byte data packet. This input serves to put a 0 into shiftregister 171. This particular signal is used to provide a referencepoint from which the type of packet which is currently being transmittedcan always be determined. The other input to shift register 171 is thebyte strobe signal, BS, which is supplied by byte disassembler 40 eachtime it requests a new byte to be transferred from the memory 152. The 0bit that is inserted in the left side of shift register 171 isright-shifted each time the byte strobe signal occurs.

After shift register 171 has been right-shifted twice, once for the D₃₆and D₃₇ byte strobes, the next byte strobe will be the beginning of asignal packet. Since the third through the sixth output taps of shiftregister 171 are connected to NAND gate 171B, the output of this gate,which is applied to two-bit comparator 173, is a 1 when a signal packetis being processed by byte disassembler 40.

A 0 on the third output tap of shift register 171 indicates that thefirst byte of a signal packet is being processed while a 0 on theseventh output tap of shift register 171 indicates that the first byteof a data packet is being processed. Thus the output of NAND gate 171Ais a 1 when the first byte of a packet is being processed. The outputsof NAND gates 171A and 171B are applied to the two-bit comparatorcircuit 173. Comparator circuit 173 also receives input from register174 which serves as a holding register for memory 167 in the same mannerthat register 156 serves as a holding register for memory 152.Comparator circuit 173 thus serves to compare the packet type and bytenumber which is currently being processed by byte disassembler 40 withthe packet type and byte number which are currently resident in register156.

When these inputs are the same, comparator 173 supplies an output signalthrough gate 175 to six-bit counter 176. Gate 175 is a four-input ANDgate having 2 of its inputs inverted by inverters 175A and 175B. Thusthe output signal from comparator 173 passes through gate 175 to counter176 at the proper time as determined by the inputs to gate 175 which aresupplied by flip-flop 172, NAND gate 146, and comparator 166. The outputof gate 175 causes counter 176 to be incremented. Counter 176 serves asan address counter which keeps track of the current address in memories167 and 152 from which the byte disassembler 40 is reading in a manneranalogous to that in which counter 168 keeps track of the address intowhich control computer 30 is writing.

Memory 152 comprises thirty-two memory words each containing sixteenbits. However, since it is desired to read each of these words out tobyte disassembler 40 in eight-bit bytes, it is necessary to alternatereading out one-half of the memory on the eight lines 155 and readingthe other half of the memory on the eight lines 154. This alternatereading is accomplished by means of flip-flop 172 and OR gates 177 and178.

Flip-flop 172 receives its clocking input from the BS signal line ofbyte disassembler 40. Thus flip-flop 172 serves to divide the bytestrobe pulses into two pulse trains, one pulse train appearing on the Qoutput of flip-flop 172 and the other on the Q output of flip-flop 172.These two pulse trains are applied respectively, to OR gates 177 and178; the Q output of flip-flop 172 being applied to OR gate 178, and theQ output of flip-flop 172 being applied to OR gate 177. The outputs ofthese two gates go to the "Select" inputs on the aforementioned memorycircuits.

The memory circuits which comprise memory 152 are characterized in thatthe contents of the currently selected addressed location are availableas the output whenever the select signal is given. Since the selectsignals are given in an alternating fashion by the outputs from OR gates177 and 178, register 156 is loaded first from one-half of memory 152and then from the other half, and then, in the following time period,from the first half again. Thus it is seen that register 156 is loadedby alternate bytes of each word that is output from memory 152.

The outputs of six-bit counters 176 and 168 are applied to memories 167and 152 by means of select circuit 179. For simplicity, only onedetailed portion of select circuit 179 has been shown in FIG. 5B. inactuality, circuit 179 comprises five sets of circuits 179A through179E. Each of these comprises, as shown in detail in circuit 179A, ANDgates 180, 181, OR gate 182 and inverter 183 that are shown in FIG. 5B.That is, the circuit 179A comprises the circuitry needed to gate one bitof the five least significant bits from each of counters 176 and 168 tothe five-bit address inputs of the two memories. AND gate 181 has as itsinputs a bit from counter 176 and the Q output of flip-flop 158. Thuswhenever flip-flop 158 is reset, which occurs during the time which isallocated for byte disassembler 40 to read bytes out of memory 152, ANDgate 181 has as its output one bit from counter 176. This is applied bymeans of OR gate 182 to memories 167 and 152. Thus whenever flip-flop158 is reset, the address suplied to memories 167 and 152 is thatdetermined by counter 176 which is the counter which keeps track of thecorrect location from which byte disassembler 40 should be reading. In asimilar fashion, AND gate 180 has as its input a bit from counter 168and the Q output of flip-flop 158 as inverted by inverter 183. Thus onalternate cycles of clock 186, AND gate 180 will supply a bit fromcounter 168 through OR gate 182 to the address inputs of memories 152and 167. Thus it is seen that select circuit 179 serves to applyaddresses to memories 167 and 152 in an alternating fashion, first theaddress into which control computer 30 is currently writing and then theaddress from which byte disassembler 40 is currently reading.

Six-bit comparator 166 serves to compare the outputs from counters 176and 168. When these outputs are equal, indicating that the location intowhich control computer 30 will next write is the same location fromwhich byte disassembler 40 will next read, this indicates that thememories 167 and 152 are empty and hence a signal is output on line 166Ato AND gate 175 through inverter 175B. When comparator 166 determinesthat the address from which byte disassembler 40 will next read is equalto the sum of the address into which control computer 30 has justwritten plus thirty-two, which indicates that memories 167 and 152 arefull, then an output signal will be generated on line 149 and applied torising edge trigger circuit 164. This signal will serve to inhibit thegeneration of an acknowledge command on line 165 in the manner describedhereinbefore. This is done because since the memories 167 and 152 arenow full, control computer 30 must be prevented from writing any moreinformation into them until room has been provided by means of bytedisassembler 40 reading out a word of the stored information.

Flip-flops 147 and 148 serve to synchronize the loop transmission bufferof FIGS. 5A and 5B. The T1 transmission line is a synchronous line whilethe control computer 30 is an asynchronous device. It is thus necessaryto insure that the outputs from control computer 30 are supplied to thetransmission line in the proper time sequence. The input to flip-flop147 is the byte strobe signal on line BS from byte disassembler 40. Theoutput of flip-flop 147 is copied into flip-flop 148 whenever AND gate159 generates an output. When flip-flop 148 receives its input fromflip-flop 147, this is output to NAND gate 146. The next time that gate160 generates an output, NAND gate 146 generates an output to registers174 and 156, which causes these registers to read from memories 167 and152, respectively. The outputs of these registers are then available tobyte disassembler 40. Register 174 provides its output by means ofinverter 185 and AND gates 184 and 186. Register 156 provides eight bitsof output on eight lines 151.

LOOP RECEIVE BUFFER

Continuing with the detailed description of the circuitry shown in FIG.2B, FIGS. 5D and 5E are seen to be a detailed diagram of the loopreceive buffer 66 shown in FIG. 2A. As shown in FIG. 5E, input to theloop receive buffer 66 comprises eight lines 195 from byte assembler 64.The output of the loop receive buffer comprises sixteen lines 209 whichare applied to control computer 30.

Loop receive buffer 66 performs the converse of the function performedby loop transmit buffer 34. That is, loop receive buffer 66 storeseight-bit bytes from byte assembler 64, forms them into sixteen-bitwords, and transfers them to control computer 30. This function isaccomplished through the proper control of memories 196 and 203 in thefollowing manner.

Memory 196 is a sixteen-word-by-sixteen-bit memory which can be formedfor example, from eight integrated circuit memories such as bipolar LSImemory 3101 manufactured by Intel, Inc. Under the control of the logiccircuitry shown in FIGS. 5D and 5E, eight-bit bytes are written intomemory 196 from byte assembler 64 while, on alternate byte strobesignals from byte assembler 64, sixteen bit words are read out of memory196 into sixteen bit register 197 from whence they are clocked out tocontrol computer 30. The manner in which the control logic accomplishesthis is as follows.

Clock 198 provides the basic timing for the loop receive buffer. Thisclock comprises an astable multivibrator which runs at a 5 megahertzrate. The output of clock 198 is applied to flip-flop 199 which is atriggered flip-flop, that is, it changes state each time it receives apulse from clock 198. Flip-flop 199 serves to divide the pulse trainfrom clock 198 into two pulse trains operating at one-half the frequencyof clock 198. The Q output of flip-flop 199 is applied to AND gate 200while the Q output of flip-flop 199 is applied to AND gate 201.Additionally, each of these two gates have as their second input theoutput from clock 198. Thus the outputs from AND gates 200 and 201 areseen to be two 2.5 megahertz pulse trains that are 180 degrees out ofphase. The pulse train that is output by AND gate 201 is used to writeeight-bit words from byte assembler 64 into memory 196, while the outputfrom AND gate 200 is used to read sixteen-bit words from memory 196 toregister 197, from which it is available to control computer 30.

The output of AND gate 201 is applied to NAND gate 202. The other inputto gate 202 is the Q output of flip-flop 225. Flip-flop 225 inconjunction with flip-flop 204 serves to synchronize the operation ofloop receive buffer 64 with the timing of the T1 transmission line inthe same manner as flip-flops 147 and 148 shown in FIG. 5A serve tosynchronize the loop transmit buffer 34 with the T1 transmission line.Thus the timing pulse from gate 201 is applied by gate 202 to the writeinput of memories 196 and 203 immediately after the byte strobe signalis applied from byte disassembler 64 on line BS.

The address into which the current byte from byte assembler 64 will bewritten is determined by five-bit counter 205. The particular byte ofthat address into which the current output from byte assembler 64 willbe written is determined by gates 206 and 207 under the control offlip-flop 208. This determination is exactly analogous to that made bygates 177 and 178 under the control of flip-flop 172 which is shown inFIG. 5A. That is, the incoming bytes are placed in alternate bytes ofthe word.

Counter 205 is incremented by the output from NAND gate 202 providedthat it is not inhibited by the output of NAND gate 219. The inputs togate 219 are derived from ten-bit shift register 211.

One input to shift register 211 is the byte strobe signal which issupplied on line BS by byte assembler 64 each time it sends an eight-bitbyte out on lines 195. The other input to shift register 211 is the D₃₆pulse, which when applied through inverter 212 puts a 0 into shiftregister 211. The D₃₆ pulse is emitted by byte assembler 64 each time itsends the thiry-seventh byte of a thirty-eight byte data packet. Thisparticular signal is used to provide a reference point from which thetype of packet currently being transmitted can be easily determined. The0 bit that is inserted in the left side of shift register 211 isright-shifted each time the byte strobe signal occurs. The output tapsof the register are used as follows.

After shift register 211 has been right-shifted twice, once each for theD₃₆ and D₃₇ byte strobes, the next byte strobe will be the beginning ofa signal packet. Thus the third output tap in FIG. 5D, is connected bymeans of inverter 200 to the K input of JK flip-flop 208. The outputs offlip-flop 208 are applied to OR gates 206 and 207 which drive the"Select" inputs of memory 196 and thus serve to write eight-bit bytesinto alternate halves of a memory word in the same manner that OR gates177 and 178 shown in FIG. 5B serve to read alternate halves of words outof memory 152.

The fourth output tap of the shift register 211 signifies the secondbyte in a signal packet. This is applied through inverter 213 to OR gate215. If a signal is simultaneously present on the READ input line,indicating that the current packet is not an empty one, then AND gate218 will transfer a 1 to memory 203. The eighth output tap of register211, which signifies the second byte in a data packet, is also appliedto OR gate 215 by means of inverter 214. Thus it can be seen that ANDgate 218 will transfer a 1 bit to memory 203 whenever the second byte ofeither a signal or data packet that is not empty is being stored inmemory 196.

NAND gate 216 has as its inputs the third through tenth output taps ofshift register 211. NAND gate 216 thus only has an output when any oneof the signals on these output taps are 0's. This corresponds to thefour bytes of a signal packet and the first four bytes of a data packet.This information is all control information used by the system in themanner discussed hereinbelow and hence the output of NAND gate 216 istransferred on line 223 to memory 203.

Memory 203 is addressed by select circuit 227 which is driven byfive-bit counters 205 and 226. Counter 205 controls the address intowhich byte assembler 64 writes while counter 226 controls the addressfrom which control computer 30 reads. Counter 205 is inhibited by NANDgate 219 when there is no signal on the READ input and when,simultaneously, the packet currently being processed is not the secondbyte of a signal packet and thus the write addressing of memory 196 isinhibited. Select circuit 227 is exactly the same as select circuit 179shown in greater detail in FIG. 5B and operates in exactly the samemanner to supply the correct read and write addresses to memories 203and 196.

Next consider the reading of sixteen-bit words from memory 196 intocontrol computer 30. This process is accomplished on acommand-acknowledge basis. Commands from control computer 30 aretransferred on line 237 to falling edge trigger 210. This trigger, whichis shown in greater detail in FIG. 5F, provides a strobe output to NANDgate 229 upon receipt of a command from control computer 30 unless aninhibit signal has been received from five-bit comparator 228 inaccordance with the discussion hereinbelow. The falling edge triggercircuit 210 also serves to supply an acknowledge signal to controlcomputer 30 on line 238 each time it receives a command unless it isinhibited.

FALLING EDGE TRIGGER CIRCUIT OF THE LOOP RECEIVE BUFFER

Falling edge trigger circuit 210 is shown in greater detail in FIG. 5F.In the circuit's quiescent state D-type flip-flop 231 is in the setstate and flip-flop 235 is in the reset state causing the strobe outputto be a 0 and the acknowledge output to be a 1. A strobe pulse isgenerated in response to a command being applied. Flip-flop 231 changesto its reset state the next time a clock pulse is applied to the clockinput of flip-flop 231. Since, at the time flip-flop 231 becomes resetflip-flop 235 is still reset, the output of AND gate 236 goes to a 1,thus beginning the strobe pulse output.

The trailing edge of the clock pulse that sets flip-flop 231 is coupledthrough inverter 232 to the clock input of flip-flop 235. This causesthe 0 on the Q output of flip-flop 231 to be coupled through NAND gate234 to the D input of flip-flop 235, causing the output of AND gate 236to fall, thereby terminating the strobe pulse output. The circuitremains in this state until the command line rises, at which time itreturns to its quiescent state until the command line is again dropped.

The generation of the strobe pulse output will be inhibited if a 1 isapplied to the inhibit input. Inverter 233 converts this into a 0 whichprevents NAND gate 234 from responding to the Q output from flip-flop231 when a 1 is applied to the command input. This, in turn, preventsthe acknowledge output from going to a 1.

Reterning then to FIG. 5D and 5E, NAND gate 229 is seen to be enabledwhenever the strobe signal from falling edge trigger circuit 210corresponds with the output from gate 200. When enabled, gate 229increments counter 226 and provides a clocking signal to checksumcircuit 239.

Checksum circuit 239 provides a parity-like check on the sixteen-bitwords sent to control computer 30 on lines 209. Checksum circuit 239serves to EXCLUSIVE OR sixteen data words with the checksum wordimmediately following it. This checksum word is generated when the datais sent in the manner to be described hereinbelow. In the absence oferror, the output of the circuit is zero after each seventeenth word ina data packet. The manner in which the EXCLUSIVE OR between successivebits in the same bit position in successive words is formed can best beappreciated by the following example. Consider for example, the ith bitposition of four successive words, N1, N2, N3, and N4. The EXCLUSIVE ORof the bit in the ith bit position in words N1 and N2 is formed. Theresult of this is EXCLUSIVE ORed with the ith bit position of word N3,the result of which is, in turn, EXCLUSIVE ORed with the ith bitposition of word N4. This process is continuously repeated. Forsimplicity, only one portion of checksum circuit 239 is shown in FIG.5E. Checksum circuit 239 actually comprises sixteen sets of circuits,239A through 239P. Each of these, as shown in detail in circuit 239A,comprises EXCLUSIVE OR gate gate 242 and D-type flip-flop 241. Flip-flop241 stores the result of each output from gate 242 and supplies it as aninput to gate 242 for the next word output from register 197, thusachieving the desired result. The outputs from each of gates 242 formthe sixteen lines 243 which are all inputs to OR gate 244. If any ofthese inputs are 1, indicating the presence of a checksum error, then ORgate 244 generates an error signal to control computer 30 on line 245.Checksum circuit 239 is reset to zero by NAND gate 244A when the fourthbyte of each data packet is given to control computer 30.

DATA MULTIPLEXER

Byte disassembler 40 and byte assembler 64, shown in FIG. 2B, performfunctions analogous to that performed by data multiplexer 58, also shownin FIG. 2B. In fact, a subset of the apparatus of data multiplexer 58can be used to implement byte disassembler 40 and byte assembler 64.Therefore, before discussing these latter two units, the logic diagramof data multiplexer 58 which is shown in detail in FIGS. 6A through 6Hwill be discussed. FIG. 6I shows the manner in which FIGS. 6A through 6Hare connected.

As shown, data multiplexer 58 serves as an interface between matchingunit 56 of loop access module 16, and terminal buffer 60 and interfacecomputer 62 of the terminal interface unit 17. The purpose of themultiplexer 58 is to collect the relevant data and signal packets fromthe transmission loop and to insert new ones onto the loop whencircumstances permit. The general manner in which data multiplexer 58achieves this purpose is as follows.

All of the timing for the operation of data multiplexer 58 is determinedby system clock 250, although functional control is exercised by theinterface computer 62. Transmission line bits, excluding the"keep-alive" bit, are serially clocked into shift register 251. When afull byte has been clocked into shift register 251 it may be decoded,left untouched, or removed from the shift register on a parallel basis.

Transmission is accomplished on a packet-by-packet basis. Oncetransmission of a packet commences, it continues until the entire packethas been transmitted. Transmission from terminal buffer 60 or frominterface computer 62 can occur when an empty packet is detected, orwhere the contents of a packet are removed by the terminal buffer,provided the packet type being processed by the data mltiplexer matchesthe packet type that interface computer 62 wants to have transmitted.This matching requirement must be observed because signal packets anddata packets are not interchangeable, as was discussed in connectionwith FIG. 4B. In addition, the request from interface computer 62 totransmit information must be detected by the data multiplexer before anappropriate time in order for transmission to be considered during thenext packet time interval.

In addition to the basic function mentioned above, the data multiplexerchecks for incoming bipolar violations in the T1 line format andprovides a means for pulse injection into the outgoing bit stream. Thispulse injection inserts the "keep-alive" bit into the outgoing bitstream and is also used to insert a special error format into theoutgoing bit stream at the appropriate time. This error format providesa means to signal subsequent stations on a loop that a bipolar violationhas occurred in a particular packet.

The manner in which these functions are performed by data multiplexer 58will now be described in greater detail with specific reference to FIGs.6A-6H. The order of the description below follows the order in which thevarious portions of the apparatus actually function during the typicaloperation of multiplexer 58. In order to facilitate this discussion andto provide better continuity between figures, various ones of the inputand output lines shown in FIGS. 6A-6H are labeled in accordance with thesignals which they transmit or receive.

Referring then specifically to FIG. 6C, matching unit 56 is seen toprovide a two wire input 353 to circuit 352. Circuit 352, which providesan interface between matching unit 58 and data multiplexer 58, isstandard T1 equipment obtainable under the name of Vicom 5120 DataReceive Unit. Circuit 352 provides a clocking singla (RCV CLOCK) tosystem clock 250. Circuit 352 also provides a repetitive set of eightpulses on lines D1 through D8 which correspond to the eight slots in thesubgroup in a standard T1 frame. It is to be noted that these pulsescorrespond to the line slots and not to either the bits in a byte or tothe bytes in a data packet. These bytes can be distinguished in thatthey are referred to by subscripted D's, D₀ through D₃₇. The RCV CLOCKsignal is also applied to receive flip-flop 253 which serves to read theline bits serially into shift register 251.

CLOCKS, COUNTING AND STEERING CIRCUITS OF DATA MULTIPLEXER 58

Data multiplexer 58 has one system clock 250 and three subclocks drivenfrom the system clock. System clock 250 comprises a one-shotmultivibrator which serves to regenerate the RCV CLOCK signal from thematching unit 56, and thus its output comprises a near-perfectfifty-percent duty cycle waveform. The subclocks comprise serial strobegenerator 254, parallel strobe generator 300, and status read pulsegenerator 358.

Serial strobe generator 254, which also comprises a one-shotmultivibrator, generates a pulse on the falling edge of each pulse fromsystem clock 250 which is used to strobe data serially into shiftregister 251. The pulse train from serial strobe generator 254 cannot,however, be used directly. As previously mentioned, the standard T1 lineformat includes a "keep-alive" bit in the line bit stream. In order thatthis "keep-alive" bit not be permitted into shift register 251, theserial strobe corresponding to the time at which this "keep-alive" bitappears at the input to shift register 251 must be inhibited. This isaccomplished by the strobe steering circuit 255.

The strobe steering circuit 255 has applied thereto the inverted D6output (D6) from circuit 352. This inversion is obtained by means ofinverter 261. When the D6 signal falls it serves to preset flip-flop256. When flip-flop 256 is preset, AND gate 257 is enabled and AND gate258 is disabled. Therefore the strobe signal from serial strobegenerator 254 cannot pass through gate 258. During the time that gate257 is enabled the serial strobe instead passes through gate 257 to thesixth slot error detector 262 enabling it to operate in the manner to bedescribed hereinbelow. When signal D7 is generated by circuit 352, it ispassed through inverter 355 and applied to flip-flop 256 therebyclearing it. This enables gate 258 and disables gate 257. Therefore theserial strobe generated by serial strobe generator 254 is again allowedto pass through gate 258 to shift register 251. Gate 258 is disabledonly during the time period when the serial strobe corresponding to the"keep-alive" bit appears. Therefore the "keep-alive" bit is the only bitthat is not permitted to enter shift register 251. The output of ANDgate 258 is also applied to the input of NAND gate 260. The output ofNAND gate 260 is applied to three-bit counter 263 which in turn providesits output to six-bit counter 264. The outputs of counters 263 and 264provide timing signals for data multiplexer 58. One timing signalgenerated by AND gate 361 is output on line D₃₆ to terminal buffer 60and to interface computer 62. That line is set to a 1 when counter 264contains the value 41.

NAND gate 260 inhibits the steered serial strobe from AND gate 258whenever the strobe corresponding to the framing bit occurs. This actionis analogous to that in which ther serial strobe corresponding to the"keep-alive" bit is inhibited. NAND gate 260, in conjunction withflip-flop 259, removes the pulse strobe corresponding to the framing bitin order that the framing bit will not be counted as a bit of usableinformation. Whenever the signal DF is output from circuit 352 toinverter 265, the output of the inverter, DF, goes to zero, therebypresetting flip-flop 259. During the time that the Q output of flip-flop259 is 0, the output of NAND gate 260 is 1. When the pulse D1 occursflip-flop 259 is cleard. Therefore, flip-flop 259 only inhibits NANDgate 260 for the time period in which the strobe corresponding to theframing bit occurs. It is thus seen that the output of NAND gate 260comprises a series of strobe pulses excluding those corresponding to the"keep-alive" bit and the framing bit. This pulse train is then countedusing the beginning of a master frame as a reference point. Thiscounting is initialized in the following manner.

As previously mentioned, the beginning of a master frame occurs when theframing bit is a 1 bit. Data multiplexer 58 is initialized at thebeginning of each master frame by the output of master frame reset pulsegenerator 266, which comprises an AND gate. The inputs to the masterframe reset pulse generator 266 comprise the DF pulse and the U pulsewhich is output from inverter 267. The U pulse, which is generated bycircuit 352, is normally used in standard T1 systems, as is well knownby those of ordinary skill in the art, to compare the actually receivedframing bit with the desired framing bit in order continuously to checkthat the incoming signal is correctly framed. Therefore, rather than usethe actual framing bit as a criterion for the beginning of the masterframe, the U pulse, which is a 1 when the framing bit should be a 1, isused. Thus the beginning of a master frame is not dependent upon a linebit which may be in error.

After counters 263 and 264 have been initialized by the output signalfrom master frame reset pulse generator 266, as inverted by inverter168, the output of NAND gate 260, which contains a series of serialstrobe pulses excluding those corresponding to the "keep-alive" bit andthe framing bit, is applied to the count input of three-bit counter 263.After the eighth one of these strobe pulses the output of three-bitcounter 263 will fall. At this time the eighth bit of the first byte hasbeen clocked from receive flip-flop 253 into shift register 251.Whenever output 252, the most significant bit of three-bit counter 263,falls, mode control flip-flop 271 in mode control circuit 269 is set.Flip-flop 271 had previously been cleared at the beginning of the masterframe by the output from master frame reset pulse generator 266.Flip-flop 271 comprises a triggered flip-flop and hence anynegative-going transition at the clock input will cause the flip-flop tochange state.

After the falling edge of output 252 of three-bit counter 263 occurs,the mode control flip-flop 271 output changes to a 1. Therefore, shiftregister 251 is ready to clock data in on a parallel basis before thenext serial strobe occurs if it is decided to do so. Note that modecontrol flip-flop 271 is set to the parallel mode after a completeeight-bit byte has been shifted into the shift register 251 irrespectiveof whether a parallel read-in will occur. If it is determined thattransmission will occur, the parallel read-in to shift register 251 fromselect circuit 380 will occur prior to the falling edge of system clock250. After the first byte of a packet has been completely read intoshift register 251, a comparison identification byte of the packet mustoccur.

To accomplish this identification, incoming packet status decoder 27 isused along with incoming packet status detector 273. To detect any emptypacket, the outputs of shift register 251, inverted by inverters274-281, are applied to NAND gate 282 of incoming packet status decoder272. If an empty packet is being passed through date multiplexer 58, thefirst eight-bit byte will necessarily be all 0's; therefore, since theinputs to NAND gate 282 are all the inverted outputs of shift register251, all of the inputs will be 1, thereby causing the output of gate 282to be a 0. NAND gate 283 decodes the identification number (ID) of thepacket. The outputs of shift register 251, along with the invertedoutputs of shift register 251 from inverters 274-281, are supplied totwo patch blocks 356 and 357. These patch blocks comprise supportingstructures containing terminals which are appropriately interconnectedso that when the ID of the attached terminal interface unit is presentin shift register 251, all of the inputs to gate 283 will be 1 therebycausing its output to be 0. The outputs of NAND gates 282 and 283 aresupplied to NOR gates 284 and 285, respectively of incoming packetstatus detector 273.

Soon after the start of the first byte of a newly received packet,either OR gate 286 or NAND gate 287 of transmit packet typeinitialization pulse generator 363 will output a zero-going pulse toindicate the start of a new date packet or a new sigal packet,respectively. Note that these two pulses occur while the new packet isactually being read into shift register 251. This instant of time isafter the parallel strobe corresponding to the last byte of thepreceding packet and before the parallel strobe corresponding to thefirst byte of the next packet. The outputs of NAND gate 287 and OR gate286 are applied to AND gate 288. Therefore the output of AND gate 288will be a zero-going pulse during the first byte of a received packet,whether it is a signal packet or a data packet. The output of AND gate288 is used to present flip-flop 289 and to clear flip-flops 290 and 291of incoming packet status detector 273. By presetting flip-flop 289, a 0output of either of NAND gates 282 or 283 is able to propagate throughNOR gates 284 or 285, respectively, as a 1.

The clock pulse used to clock the J input of JK flip-flops 290 and 291into the flip-flops is generated by the status read pulse generator 358which comprises a NAND gate whose inputs are the output of mode controlcircuit 269 and the output from system clock 250.

After the first byte of a new packet has been fully clocked into shiftregister 251, as after every complete byte, the mode control circuit 269output rises to a 1. At that instant however, the output from systemclock 250 is in its low state. When the output from system clock 250rises to a 1, the output of the status read pulse generator 358 falls toa 0. This output is used to clock flip-flops 289, 290, and 291 ofincoming packet status detector 273. At that time, whatever signal is onthe J inputs of flip-flops 290 and 291 is transferred into thoseflip-flops and appear on their outputs. Also at this time flip-flop 289returns to the state where its Q output is a 0 and its Q output is a 1.This is accomplished, as shown in FIG. 6E, by feeding the Q output backinto the K input. Therefore, when the output of status read pulsegenerator 358 falls, the 1 input to the K input of flip-flop 289 willcause the Q output to go to 0 and the Q output to go to 1. With the Qoutput going to 1 the outputs of NOR gates 284 and 285 remain 0 untilflip-flop 289 is again present.

The output of NOR gate 284 is applied to the J input of JK flip-flop 290and the output of NOR gate 285 is applied to the J input of JK flip-flop291. Thus if an empty packet is identified, flip-flop 290 is set so thatits Q output goes to 1. If a terminal ID is decoded satisfactorily,flip-flop 291 is set so that its Q output goes to a 1. Either flip-flopwill remain in the set state until cleared by the zero-going pulsegenerated by AND gate 288 during the start of the next packet.

When the associated terminal interface unit wishes to transmit data, thefirst thing that data multiplexer 58 must do is to find either an emptypacket in the line bit stream or a packet that is addressed to theassociated terminal interface unit. In the latter case, the terminalinterface unit removes the information in the packet addressed to itthereby leaving the packet empty.

Next interface computer 62 must apply either or both of two distinctsignals to data multiplexer 58. One signal, SENDD, indicates a requestto transmit a data packet and the other, SENDS, indicates a request totransmit a signal packet. The data multiplexer identifies these twosignals by means of request-to-send recognition circuit 292.Specifically, the SENDD signal is applied to AND gate 294 ofrequest-to-send recognition circuit 292 and the SENDS signal is appliedto AND gate 293. The other inputs to these two gates come from transmitpacket type indicator circuit 295, which comprises a flip-flop. When asignal packet is being received by the data multiplexer, the Q output offlip-flop 295 will be a 1, thereby enabling AND gate 293. When a datapacket is being received by the data multiplexer, the Q output offlip-flop 295 will be a 1, thereby enabling AND gate 294. It is thefunction of AND gates 293 and 294 to gate the SENDD and SENDS signalswith the packet type that is being received at that time. Therefore, ifsignal packet transmission is requested and the date multiplexer isreceiving a date packet, the outputs of AND gates 293 and 294 will bothbe 0 and hence the output of OR gate 296 will be 0. Therefore nooutgoing date packet or signal packet transmission will take place. Thesame holds true in the reverse situation where date packet transmittionhas been requested and a signal packet is being received. Thus, in orderto transmit a signal packet, a signal packet must be used; and in orderto transmit a date packet, a date

TRANSMISSION OF A SIGNAL PACKET BY THE DATE MULTIPLEXER

The manner in which a signal packet is transmitted by data multiplexer58 can best be appreciated by a consideration of the following example.In this example it is assumed that the SENDS signal has been received,thereby causing one input to AND gate 293 to be a 1 and, further, that asignal packet has just begun to be received. Therefore, the Q output offlip-flop 295 will be a 1 thereby causing the output of AND gate 293 tobe a 1. This 1 output, which is applied to the input of OR gate 296 willcause that gate's output to be a 1. This 1 output is applied to the Dinput of D-type flip-flop 297, which is also contained in arequest-to-send recognition circuit 292 shown in FIG. 6E. When theoutput of AND gate 288 rises, the signal on the D input of flip-flop 297will be transferred to its Q output. In this way it is insured that theSENDS signal is received and the match between received packet type anddesired type of transmission is made before there is any parallelclocking into shift register 251. This insures that there can be noerrors generated as a result of signals changing at critical times.

The Q output of flip-flop 297 of request to send recognition circuit 292is applied to transmit-enable gate 298, which comprises an AND gate. Theother input to transmit enable gate 298 comes from OR gate 299. Theoutput signal from OR gate 299, when it is a 1, indicates, as describedabove, that either an empty packet has been detected or the ID of theassociated terminal interface unit was successfully decoded. In thissituation both imputs to AND gate 298 are 1 thereby causing its outputto be a 1. The output of AND gate 298 is returned to interface computer62 as the SEND line to indicate when data is being transmitted. Theoutput of OR gate 299 is input to parallel strobe steering circuit 307.Thus when the output of OR gate 299 is a 1, a parallel strobe is appliedto shift register 251 as described below.

The timing signals for the parallel insertion of data in shift register251 are provided by parallel strobe generator 300 which comprises aone-shot multivibrator that is driven by the output of parallel strobegating circuit 301 which comprises an AND gate. To insure that theparallel strobe occurs at the proper time, one-shot multivibrator 304 isused as a delay and is triggered at the time the system clock 250 outputrises. The Q output of delay 304 is applied to one of the inputs ofparallel strobe gating circuit 301. Delay 304 will output a pulse everytime the system clock 250 output rises. However, the parallel strobe isrequired only after a complete eight-bit byte. Therefore, the Q outputof delay 304 is gated with the mode control circuit 269 output byparallel strobe gating circuit 301. Hence only when the output from modecontrol 269 is a 1 does a pulse generated by delay 304 propagate to theoutput of parallel strobe gating circuit 301. At all other times theoutput of gating circuit 301 is clamped to a 0 level by the mode control269 output being a 0. When the Q output of flip-flop 271 of mode control269 is a 1, the pulse generated by delay 304 will appear at the outputof gate 301. The falling edge of this pulse triggers the parallel strobegenerator 300. Thus it is seen that this strobe, denoted the "bytestrobe" signal, is generated after every complete eight-bit byte hasbeen completely read into shift register 251 irrespective of whethertransmission will be initiated by the terminal interface unit.

At the time that a complete byte of data has been assembled in shiftregister 251, the byte strobe from parallel strobe generator 300 clocksthe data into register 251A. The eight output lines MDI from register251A go to interface computer 62 and terminal buffer 60. At the sametime that data is clocked into register 251A, a pulse appears on line308 if the data belongs to an empty packet or if the data belongs to apacket whose ID was recognized. The pulse on line 308 strobes the outputof select circuit 380 into register 251A.

Select circuit 380 comprises eight circuits, 380A through 380H, as shownin FIG. 6B. Each of these circuits contains the gates shown in detail incircuit 380A, that is, AND gates 382, 383, 384, 385 and 389, inverters386 and 387, and OR gate 388. Each of circuits 380A through 380Hprovides one bit of the eight bits of the data supplied to shiftregister 251 as follows.

When interface computer 62 indicates that it wants to send, the outputof transmit enable gate 298 will be a 1 if transmission is actuallytaking place. That output is a 0 when there is no request to send evenif the opportunity exists. In these latter circumstances, AND gate 389is inhibited and zero bytes are strobed into shift register 251. When arequest to send has been received, and the output of gate 298 is a 1,AND gate 389 is enabled, and the source of data strobed into shiftregister 251 is determined by lines 392 and 393.

When the byte of data to be loaded into shift register 251 is the firstof a packet, then both lines 392 and 393 are equal to 1, AND gate 382 isenabled, and the data input to shift register 251 is taken from patchblock 381. Patch block 381 serves to generate the associated terminal'sID on eight lines 621.

When the byte of data to be loading into shift register 251 is one ofthe second through the fourth bytes of a packet, then lines 392 and 393are zero, AND gate 385 is enabled, and the data on the eight lines MDOfrom interface computer 62 are strobed into shift register 251.

When the byte of data to be loaded into shift register 251 is the fifththrough thirty-eighth of a data packet, then line 392 is a 1 and line393 is a 0, AND gate 383 is enabled, and the data on lines SDO fromterminal buffer 60 are strobed into shift register 251.

Line 392 is the Q output of JK flip-flop 390 which is preset at thestart of each packet by the output and AND gate 288. Flip-flop 390 iscleared by the falling edge of the output from mode control 269 which isapplied to the flip-flop's clock input. Thus flip-flop 390 remains setonly during the first byte time of a packet. When flip-flop 390 isreset, NAND gate 391 is enabled and the signal on line 393 is theinverted form of the Q output of D-type flip-flop 366. That flip-flop isreset by the output of AND gate 288 at the start of a packet. Theflip-flop 366 is set when the output of NAND gate 365 rises. This occurswhen counter 264 contains the valve 8, and the most significant bit ofcounter 263 falls to zero.

The byte strobe signal output by parallel strobe generator 300 isapplied to gates 305 and 306 of parallel strobe steering circuit 307,and is also applied to interface computer 62 by line BS where it is usedas a timing reference for the interface computer 62 as describedhereinbelow. If, as in the case previously descussed, the output of ORgate 299 is a 1, then AND gate 305 is enabled and the parallel strobe isallowed to propagate through it. The output of AND gate 305 is appliedto the parallel load clock input 308 of shift register 251 where aparallel read-in to shift register 251 takes place. If, on the otherhand, the output of OR gate 299 is a 0, then AND gate 305 will bedisabled and AND gate 306 will be enabled. The strobe signal generatedby parallel strobe generator 300 will then be allowed to propagatethrough AND gate 306 but not through AND gate 305 and the parallel loadclock input 308 of shift register 251 will not be strobed. The outputsof AND gates 305 and 306 are applied to the input of OR gate 309. Theoutput of OR gate 309 comprises the parallel strobe pulse irrespectiveof whether transmission has been enabled or not. The output of OR gate309 is fed back to the input of OR gate 270 in mode control circuit 269where it causes the Q output of mode control flip-flop 271 to return toits 0 state, thereby preparing shift register 251 for serial operationduring the next incoming byte. During this time the byte present inshift register 251 is serially shifted out of the shift register throughthe injector circuit 302 to the transmit flip-flop 303 and out onto theline.

Turning then to injector circuit 302 shown in FIG. 6G, this circuit isseen to provide the means for inserting bits into the serial bit streamto comply with system constraints. It inserts the "keep-alive" bit intothe sixth slot of a line subgroup, and it also inserts an error formatinto the bit stream whenever the transmit error steering circuit 310indicates that it should do so. This error format comprises a 1bit inevery line slot except for the "keep-alive" slot, which contains a 0 inthis format. The framing bit, however, is allowed to pass throughinjector circuit 302 in its original state without being altered in anyway.

Consider now a case of normal transmission where the error format is nottransmitted. In this situation the output of OR gate 311 of transmiterror steering circuit 310 will be a 0, thereby causing the output ofNAND gate 312 of interior circuit 302 to be a 1. Flip-flop 313 and ORgates 314 and 315 are used to insert the "keep-alive" bit into the bitstream. During times other than those when the "keep-alive" bit is to beinserted, the outputs of both of OR gates 314 and 315 will be 1. In thissituation inputs 317, 318, and 319 to NAND gate 320 are 1. Input 316 isfrom the output of inverter 281 which inverts the output of the lastcell of shift register 251. Therefore, the output of NAND gate 320 is 1.Hence, the output of NAND gate 320 is seen to be in the same state asthe last call of shift register 251. The output of NAND gate 320 ispassed to the input of AND gate 322. The other input to AND gate 322comes from OR gate 323. Since one of the inputs to OR gate 323 comesfrom the output of NAND gate 312, which is a 1 when the error format istransmitted, the output of OR gate 323 will be a 1 thereby enabling ANDgate 322 and passing the output of NAND gate 320 through AND gate 322 totransmit flip-flop 303. On each falling edge of system clock 250 theoutput of AND gate 322 is clocked into transmit flip-flop 303 where itis sampled during the next 1 state of system clock 250. A furtherdescription of the operation of transmit flip-flop 303 in conjunctionwith bipolar converter 324 is contained hereinbelow.

Consider now the injection of the "keep-alive" bit into the bit stream.First considering the normal situation, that is, the situation thatapplies to every "keep-alive" time slot except the one immediatelyfollowing the framing bit. In this normal situation the set output offlip-flop 313 of injector circuit 302 is a 0, which holds the output ofOR gate 315 to a 1. When the set output of flip-flop 313 is 0, theoutput of OR gate 314 will be a 1 whenever its input from inverter 355,that is D7, is 0. D7 is a 1 at all times except for when it falls to 0for one system clock time. Therefore when the D7 pulse occurs, theoutput of OR gate 314 will go to a 0, causing the output of NAND gate320 to go to a 1 and the output of AND gate 321 to go to a 0. Since, asstated above, the output of NAND gate 312 is at this time a 1, theoutput of AND gate 322 will also be a 1. Therefore a 1 will be clockedto transmit flip-flop 303 on the falling edge of system clock 250.

Next considering the situation of injection immediately after receivinga framing bit, it can be seen that the "keep-alive" bit injected byusing the pulse D7 would cause the "keep-alive" bit to be injected intothe time slot immediately following the desired one. In this particularsituation the D6 pulse is used. Note that the time slot referred toprecedes the transmission of the framing bit by data multiplexer 58. TheDF pulse is used to preset flip-flop 313 of injector circuit 302. Withthe Q output of flip-flop 313 a 1, the output of OR gate 314 will be a1, and with the Q output a 0, the output of OR gate 315 will depend uponD6. When the pulse D6 goes to 0, the output of OR gate 315 will go to 0.With the output of OR gate 315 at 0, the output of NAND gate 320 is a 1,and the output of AND gate 322 is a 0. The output of OR gate 323 andNAND gate 320 each a 1 causes the output of AND gate 322 to be a 1. Theoutput of AND gate 322 is clocked into transmit flip-flop 303. Using thepulse D6 in this situation causes the "keep-alive" bit to be inserted inthe proper line time slot, the sixth slot. Two system clock pulseperiods after pulse D6 occurs, pulse D8 occurs, D8 being used to clearflip-flop 313. The clearing of flip-flop 313 inhibits OR gate 315,therefore pulse D7 will again be the pulse that inserts a 1 into the"keep-alive" slot until the next framing bit is received.

TRANSMISSION OF THE ERROR FORMAT BY THE DATA MULTIPLEXER

When the output of OR gate 311 of transmit error steering circuit 310 isa 1, the error format is transmitted. In this format all the bit slotsexcept the "keep-alive" bit slot contain 1's and the "keep-alive" bitslot contains a 0. In order to preserve synchronization in the system,the framing bit is allowed to propagate through the injector circuit 302without alteration.

Assume now that no transmission has been initiated and that thereforethe transmit error disable circuit comprising flip-flop 325 has not beenset to inhibit the error format. The Q output of flip-flop 325 is thena 1. The remaining input to NAND gate 312 comes from the output of ORgate 326. Assuming for the moment that flip-flop 327 is in its resetstate, then the output of OR gate 326 is a 1. Therefore, since the threeinputs to NAND gate 312 are all 1, the output of the gate is a 0. Thiscauses the output of NAND gate 320 to be a 1. Except at those times whena signal is injected into the "keep-alive" slot through OR gates 314 or315, the output of both of these gates is a 1. Since both of the inputsto AND gate 321 are 1, its output is a 1 thereby causing the output ofOR gate 323 to be a 1. Since both inputs to AND gate 322 are also 1, itsoutput is a 1. Hence a 1 level is applied to transmit flip-flop 303 tobe clocked into it on the falling edge of the next pulse from systemclock 250.

Now consider the "keep-alive" slot. As previously described, the D7pulse normally causes a 1 to be inserted into the "keep-alive" slot. Inthis situation, when the D7 pulse goes to 0, thereby causing the outputof OR gate 314 to go to 0, the corresponding input to AND gate 321 goesto 0, and therefore the output of AND gate 321 will be a 0 for the timethat the D7 pulse is present. With the output of NAND gate 312 a 0, andthe output of OR gate 314 a 0, both inputs to OR gate 323 are 0 therebycausing its output to be 0. Thus one input to AND gate 322 is 0 whichcauses its output to be a 0. A 0 is thereby clocked into transmitflip-flop 303 at the time of the occurrence of the "keep-alive" slot. Aspreviously described, immediately, following the receipt of a framingbit, the "keep-alive" bit must be generated one slot earlier than usualin order that it be in the correct line time slot. This is accomplishedby presetting flip-flop 313 by using the DF pulse. This, therefore,enables OR gate 315 and disables OR gate 314. Note that in this context"enable" means applying a 0 input to OR gate 315. When the D6 pulseappears from inverter 261, the output of OR gate 315 goes to 0, causingthe output of AND gate 321 to go to a 0, thereby making one input to ORgate 323 a 0. Since the other input to OR gate 323 comes from NAND gate312, whose output is also a 0, the output of OR gate 323 is a 0. Thusthe output of AND gate 322 will also be a 0 and a 0 will be clocked intothe "keep-alive" time slot. As soon as the D8 pulse occurs, flip-flop313 is cleared so that until the framing bit occurs again the D7 pulsewill be used to fill the "keep-alive" slot.

Another special situation occurs when the framing bit is clocked intoshift register 251. In order to preserve line synchronization, it isnecessary to transmit the framing bit exactly as it was received withoutregard to the action of injector circuit 302. Note that one of theinputs to NAND gate 312 comes from the output of gate 326, which is a 1.

In the normal situation, flip-flop 327 is in its reset state with its Qoutput equal to 1. The Q output of D-type flip-flop 327 is fed back toits D input so that when the clock lead is pulsed the Q output of theflip-flop will go to 0. The input to the clock lead of flip-flop 327comes from the Q output of flip-flop 313. The DF pulse presets flip-flop313 to allow the unaltered framing bit to pass through injector circuit302 and the following D8 pulse clears it. When the D8 clear pulseoccurs, the Q output goes from a 0 to a 1. This 0 to 1 transition causesthe signal on the D input of flip-flop 327 to transfer to the Q outputof flip-flop 327 and its complement to the Q output. Therefore on the D8pulse immediately following the DF pulse the Q output of flip-flop 327is fed to one input of OR gate 326.

The other input to gate 326 is from the D1 pulse which is output frominverter 328. This pulse is normally a 1 except during the time of theD1 time slot at which time it is a 0. When the D1 pulse does go to 0,and with the other input to OR gate 326 also a 0, the output of OR gate326 also goes to 0. This 0 signal applied to the input of NAND gate 312causes the output of NAND gate 312 to be forced to a 1. With the outputof NAND gate 312 a 1 and the output of both gates 314 and 315 a 1,inputs 317, 318 and 319 of gate 320 are 1. With the output of NAND gate312 a 1 the output of OR gate 323 is also a 1, therefore AND gate 322 isenabled and the inverted output of the end cell of shift register 251,which is the framing bit, is transferred on input line 316 to NAND gate320 where it is inverted again and passes through AND gate 322 totransmit flip-flop 303. Hence at the next clock pulse from system clock250, the unaltered framing bit is transmitted.

When flip-flop 313 is cleared by the D8 pulse, the output of OR gate 314returns to its normal 1 value, thereby removing the inhibit from NANDgate 312 and returning the injector circuit 302 to the previouscondition whereby the 1 bit error signal from OR gate 311 causes theoutput of NAND gate 312 to be 0, thereby causing the error format to beproperly injected into the bit stream.

TRANSMIT ERROR DISABLE

When transmission is initiated by a terminal interface unit it isdesired that incoming errors do not cause injector circuit 302 to outputa signal to transmit flip-flop 303 indicating that errors were received.When transmission is to be initiated, it is undesirable and unnecessaryto send out only an error format. The transmit error disable circuit325, which comprises a flip-flop, inhibits transmission of the errorformat in this case as follows.

Whenever the output of OR gate 299 is a 1, this 1 output is applied tothe D input of D-type flip-flop 325. This 1 input causes the Q output offlip-flop 325 to fall to 0 upon being clocked by the rising edge ofparallel strobe generator 300. This 0 input is applied to NAND gate 312and causes the output of NAND gate 312 to remain a 1 as long as the Qoutput of flip-flop 325 is a 0. This inhibits the transmission of theerror format by transmit flip-flop 303.

Once flip-flop 325 has been set, it remains in that state until thefirst parallel strobe associated with the next packet occurs. At thattime, if no transmission is to be made, the output of OR gate 299 willbe 0. This 0 is applied to the D input of D-type flip-flop 325 andcauses its Q output to go to 0 and its Q output to go to 1 when thefirst parallel strobe associated with the next data packet occurs. Sincethe reset output of flip-flop 325 is one of the inputs to NAND gate 312,the output of NAND gate 312 will now be determined by its other twoinputs.

TRANSMIT FLIP-FLOP AND BIPOLAR CONVERTER OF THE DATA MULTIPLEXER

As shown in FIG. 6G, the output of AND gate 322 of injector circuit 302is applied to the input of flip-flop 303 the tansmit flip-flop. Witheach falling edge of system clock 250, the output of AND gate 322 isclocked into transmit flip-flop 303. Once a bit has been clocked intothis flip-flop no further insertions or changes can be made. The outputof flip-flop 303 is fed to AND gate 329 of biopolar converter 324.

Bipolar converter 324 converts the unipolar logic level of the datamultiplexer to a line-compatible bipolar signal. The output of flip-flop303 that was clocked in on the falling edge of system clock 250 issampled by AND gate 329 during the next clock pulse interval. If a 1 bitwas clocked into flip-flop 303 the output of AND gate 329 is a 1 duringthe next clock pulse interval. If a 0 was clocked into flip-flop 303 theoutput of AND gate 329 is a 0 during the next clock pulse interval. Inthe case where the output of AND gate 329 is a 0, both AND gates 331 and332 will have 0 output thereby causing both of transistors 334 and 335to be off. With these transistors both off, zero volts will appearacross the secondary winding of transformer 336. In the situation wherethe output of AND gate 329 is a 1, the output of either AND gate 331 or332 will be a 1 causing transistor 334 or 335, respectively, to turn onduring the duration of the system clock pulse. This action causes eithera positive or negative pulse to appear at the secondary winding oftransformer 336.

Flip-flop 330 causes adjacent one-bit line pulses to be of oppositepolarity. Assume, for example, that the Q output of flip-flop 330 is a1, thereby enabling AND gate 331. When the system clock pulse falls, theoutput of AND gate 331 falls, thereby causing flip-flop 330 to change toa state where its Q output is a 1. AND gate 332 is now enabled for thenext 1 bit that is to be transmitted. Since flip-flop 330 requires afalling edge to change state, it will only change state after a 1 bithas been transmitted. In this manner adjacent 1 bits on the line will beof opposite polarity.

ERROR DETECTION

Error detection occurs in two different circuits in data multiplexer 58.First, there is an error detector that detects the 1 bit inserted in the"keep-alive" slot. The output of receive flip-flop 253 is applied to theinput of inverter 337 of six-slot error detector 262. The output ofinverter 337 is fed to the D input of flip-flop 338. When the signal inthe "keep-alive" slot is a 1, the output of inverter 337 will be a 0thereby applying a 0 to the D input of flip-flop 338. When the signal inthe "keep-alive" slot is a 0, the output of inverter 337 will be a 1,thereby applying a 1 to the D input of flip-flop 338.

The clock for flip-flop 338 comes from the strobe steering circuit 255,which supplies a clock pulse to the clock input of flip-flop 338corresponding to the "keep-alive" slot only as has been previouslyexplained. A 0 input clocked into the flip-flop will cause its Q outputto apply a 1 to the input of AND gate 339, thereby indicating an error.

The other error detecting circuit is the PCM error detecting circuit inreceive unit 352. This circuit outputs a PCM ERROR pulse whenever thebipolar nature of the incoming signal has been violated by two adjacent1 bits being of the same polarity. The pulse is of the same width and inthe same position as a line pulse that violates the bipolar code. ThePCM ERROR pulse is aplied through inverter 340 to the other input of ANDgate 339. Under normal conditions the output of inverter 340 is a 1.When an error is detected, its output will go to 0. When either of thetwo inputs to AND gate 339 go to 0, thereby corresponding to an error,the output of AND gate 339 goes to 0.

The output of AND gate 339 is applied to one input of OR gates 341 and342 of incoming packet type detector and steering circuit 343. The otherinput to these two gates comes from flip-flop 344, which steers theerror signal to the proper one of OR gates 341 and 342. It is importantthat the packet type, either signal or data, in which the error wasdetected be noted so that the correct packet will be made to contain theerror format when it is transmitted. Flip-flop 344 indicates which typeof packet is currently being received. It derives its preset signal fromNAND gate 345. The inputs to NAND gate 345 are the pulse D8 and outputs264A, 264D and 264F of six-bit counter 264 and output 252 of three bitcounter 263. When the output of NAND gate 345 falls to 0, therebypresetting flip-flop 344, a 0 input to OR gate 341 corresponding to adetected error is allowed to propagate to its output. Note thatflip-flop 344 is preset and set using the digit pulse corresponding tothe last time slot in the packet.

In order to insure that a PCM error detected in the first bit of a newpacket is directed to the flip-flop corresponding to that new packet, itis necessary to use the digit pulse corresponding to the last line bitof the previous packet. The appropriate steering is provided byflip-flop 344.

When flip-flop 344 is in the preset state, any errors detected andthereby output as a 0 by AND gate 339 will be directed through OR gate341 to flip-flop 346 in incoming error detector 347. The 0 signal willserve to preset flip-flop 346 thereby indicating that there was an errorin the incoming signal packet. Flip-flop 346 will remain in this stateuntil the signal packet has been completely transmitted out of shiftregister 251. In the same manner, when flip-flop 344 is in the resetstate as a result of NAND gate 348 applying a 0 pulse to its clearinput, its Q output will be 1. Therefore any 0 output of AND gate 339will propagate through OR gate 342 to preset flip-flop 349.

Since it is possible that an error may be detected in the first byte ofa new incoming packet while the last byte of the previous packet isstill being transmitted, the error format is not transmitted until thenew packet is being transmitted. This is insured by the action oftransmit error steering circuit 310. Flip-flop 350 forms the basis ofthis circuit. The JK inputs to this flip-flop come from the Q and Qoutputs, respectively, of flip-flop 295. Flip-flop 295 indicates thetype of packet that will be transmitted starting with the serial strobefollowing the next parallel load strobe. The clock pulse of flip-flops350, 346, and 349 is derived from the Q output of flip-flop 289 inincoming packet status detector 273. Flip-flop 289 is normally in thereset state. The output of gate 288, which is a zero-going pulse toindicate the start of a new data packet or a new signal packet, isapplied to the preset input of flip-flop 289. This action occurs afterthe last parallel load strobe of the previous packet and before thefirst parallel load strobe of a new packet.

The output of the status read pulse generator 358 is applied to theclock input of flip-flop 289. When the output of status read pulsegenerator 358 falls, which action precedes the parallel load strobecorresponding to the first byte of a new packet, the Q output offlip-flop 289 will go to 0. This is the result of tying the Q outputback to the K input with the J input grounded. The falling edge of the Qoutput is the clock for flip-flops 346, 349, and 350. The time at whichthis happens is immediately preceding the parallel load strobecorresponding to the first byte of a new packet. The transmit errorsteering circuit 310 will therefore have time to settle and to apply theproper signal to injector circuit 302 in time for the next serial strobeto shift register 251. The output of transmit error steering circuit 310is also applied to interface computer 62 on line BPER.

Flip-flop 350 has the secondary function of providing the means to clearflip-flops 346 and 349 at the appropriate time. For example, assume thatan error is detected in the signal packet thereby causing flip-flop 346to preset at the appropriate time. Also assume that signal packettransmission has been completed and data packet transmission is about tostart. Therefore, sometime between this time and the time the nextsignal packet is received, flip-flop 346 must be cleared so that if nonew signal packet errors are detected, the next signal packet can betransmitted without the error format. To accomplish this, the Q outputof flip-flop 350 is applied to the K input of flip-flop 346. Likewise,the Q output of flip-flop 350 is applied to the K input of flip-flop 349to accomplish this same clearing function for the data packet.

Assume further that the data multiplexer 58 has just completedtransmitting the signal packet in which the Q output of flip-flop 350 isstill high. When the clock for flip-flops 350, 346, and 349 occurs,which is prior to the parallel load strobe corresponding to the firstbyte of a packet, the 1 on the Q output of flip-flop 350 is fed back tothe K input of flip-flop 346 causing flip-flop 346 to go to the statewhere its Q output is 0. Therefore flip-flop 346 is cleared ready toreceive an error signal on its preset lead at the next time that asignal packet is being received. The same situation holds true when adata packet is being transmitted. The Q output of flip-flop 350 will bea 1 and the Q output of flip-flop 350 will be a 0. Therefore when theclock pulse generated by flip-flop 289 of incoming packet statusdetector 273 occurs, the 1 output of flip-flop 350 on its Q output thatis fed back to the K input of flip-flop 349 will cause flip-flop 349 toclear itself and be ready to accept an error signal on its preset leadthe next time that a data packet is being received.

As mentioned above, a subset of the apparatus comprising datamultiplexer 58 can be used to implement byte disassembler 40 and byteassembler 64. The inputs to and outputs from data multiplexer 58 havebeen labeled A through E in FIG. 2B and in FIGS. 6A-6H to facilitate thefollowing discussion.

BYTE DISASSEMBLER

Turning then to byte disassembler 40, this device can be made from theapparatus shown in FIGS. 6A-6H by connecting the eight lines 38 shown inFIG. 2B to the eight lines labeled "C" in FIG. 6B, and by connecting thepair of wires labeled "B" in FIG. 6G to terminal matching unit 42 shownin FIG. 2B. Lines A, D and E shown in FIGS. 6C, 6B, and 6A are not usedby byte disassembler 40. Additionally, since byte disassembler 40 musttransmit all packets it receives rather than merely those having aparticular identification number, patch blocks 356 and 357 shown in FIG.6A must be reconfigured so as to match any zero or non-zeroidentification number. Further, flip-flop 390 shown in FIG. 6F must bereplaced by a patch block configured so that the signals appearing onlines 394 and 392 are each a 0.

BYTE ASSEMBLER

Byte assembler 64 can be made from the apparatus shown in FIGS. 6A-6H byconnecting the eight lines labeled "E" in FIG. 6A to loop receive buffer66 shown in FIG. 2B and by connecting the pair of wires labeled "A" inFIG. 6C to terminal matching unit 42 shown in FIG. 2B. Lines B, C, and Dshown in FIGS. 6B and 6C are not used by byte assembler 64.Additionally, since byte assembler 64 must transmit all packets withnon-zero identification numbers that it receives rather than merelythose having a particular identification number, patch blocks 356 and357 shown in FIG. 6A must be reconfigured to match any non-zeroidentification number. Further, the output of NAND gate 282 must beapplied to patch block 356.

TERMINAL BUFFER

Terminal buffer 60 of terminal interface unit 17 shown in FIG. 2B isshown schematically in FIG. 7A. As shown in FIG. 7A, terminal buffer 60comprises four major parts: data receive buffer 450, data transmitbuffer 451, channel select circuit 452, and channel break circuit 453.

Data receive buffer 450 receives data from data multiplexer 58 on eightlines MDI and transfers it to digital device 18 by means of eight lines455. Data receive buffer 450 assembles a complete packet of data beforeany of it is made avaiable to digital device 18.

Similarly, data transmit buffer 451 receives data from digital device 18on eight lines 456 and transfers it to data multiplexer 58 on eightlines SDO. Again, a complete packet of data is assembled before it istransmitted.

Channel select circuit 452, in response to a command on eight lines 458from digital device 18, selects a channel for the data transmission andpasses this information to interface computer 62 on eight lines SBC.

Finally, channel break circuit 453 transfers a signal from interfacecomputer 62 on eight lines RCH that notifies digital device 18 about achange in status of a non-selected channel. This information istransferred to digital device 18 by eight lines RCH.

Each of the four functional units 450, 451, 452, and 453 of terminalbuffer 60 operates under the control of both digital device 18 andinterface computer 62. The manner in which this control is exercised andthe manner in which each of the major blocks shown in FIG. 7Aaccomplishes its function may best be appreciated by means of FIGS.7B-7F which illustrate terminal buffer 60 in greater detail.

FIG. 7B illustrates the timing signals used in the operation of terminalbuffer 60.

Timing signals for the entire terminal interface unit 17 are generatedby data multiplexer 58 and transmitted to terminal buffer 60 andinterface computer 62. The key timing signal is the byte strobe signalappearing on line BS in the data multiplexer logic diagram of FIG. 6E.This strobe occurs forty-two times during each master frame andcoincides with the complete assembly of one eight-bit byte in register251A of data multiplexer 58. At the time data multiplexer 58 issues abyte strobe it puts the eight-bit byte of data into register 251A andsimultaneously reads data from one set of its data input lines, eitherMDO or SDO. When the first four byte strobes in a master frame occur,the four eight-bit bytes of the signal packet are put on the data outputlines MDI, and when the subsequent thirty-eight byte strobes in onemaster frame occur the thirty-eight bytes of a data packet are put onthe data multiplexer output lines MDI. The time interval following onebyte strobe is identified by the name of the byte which for that timeinterval is available on the eight data multiplexer output lines MDI.The four time intervals during which the four bytes of a signal packetare available are known respectively as S₀, S₁, S₂, and S₃. Thethirty-eight time intervals during which the thirty-eight bytes of adata packet are available are known respectively as D₀, D₁, et cetera,through D₃₇. Each of these time intervals starts when the byte strobeoccurs and ends just before the occurrence of the next byte strobe.

DATA RECEIVE BUFFER

FIG. 7C is a logic diagram of data receive buffer 450 shown in FIG. 7A.This unit assembles and stores the thirty-two bytes of data from a datapacket in response to a pulse being applied on line RCV to flip-flop468. This pulse occurs during time period D₃ and causes data receivebuffer 450 to read thirty-two bytes of data from the eight input linesMDI and to store them in memory unit 466 during time periods D₄ throughD₃₅. Memory unit 466 comprises a thirty-two-word-by-eight-bit memory.

Concurrently with the store operation, the signals on lines MDI areapplied to checksum circuit 467 which accumulates the logical sum of theincoming data and compares it with the sixteen-bit sum received on inputlines MDI during time periods D₃₆ and D₃₇. If the checksum is found tobe in error, then the error signal output from circuit 467 will be a 1,otherwise it will be a 0.

Checksum circuit 467 utilizes the apparatus of checksum circuit 239shown in FIG. 5E. The input to checksum circuit 239 comprises sixteenbits while the input to checksum circuit 467 comprises eight bits. Thusin order for checksum circuit 467 to compute a sixteen bit checksum, thesixteen EXCLUSIVE OR gates 242 and flip-flops 241 of checksum circuit239 are divided into two groups of eight and the eight lines MDI arealternatively gated to each of these two groups through the use of theleast significant bit from counter 469 on line 454. The manner in whichchecksum circuit 239 shown in FIG. 5E can be adapted to serve aschecksum circuit 467 will be apparent to those of ordinary skill in theart from the above discussion.

Incoming data bytes D₄ through D₃₅ are stored in successive locationswithin memory unit 466 as determined by the output of counter 469. Thiscounter is initialized by the five lines which are the most significantbits of the eight lines RBL at the same time that command pulse RCV isissued to flip-flop 468 by interface computer 62. Once the data has beenassembled in receive buffer memory 466, an RCLEAR pulse is given to JKflip-flop 468 which causes the assembled data to be made available todigital device 18 on the eight data lines 455. Counter 469 is againinitialized when the RCLEAR pulse is applied to flip-flop 468, and thevalue then used is the same as the value used to initialize the counterwhen the RCV pulse is issued.

Digital device 18 obtains data eight bits at a time over the eight datalines 455 in response to commands which it issues to falling edgetrigger circuit 470 on line RD CMD. Falling edge trigger circuit 470,which is identical to circuit 210 shown in FIG. 5D, acknowledges thecommands issued on line RD CMD on line RD STS. The digital device isallowed to read eight-bit data bytes from memory 466 until counter 469generates an overflow signal on line RSUM at which time the receivecycle is repeated. Digital device 18 receives an end-of-message signalfrom AND gate 472 on line EOMR when the last byte of information is readfrom memory 466. That signal will be set if, when the preceding RCVpulse was applied to flip-flop 468, the input line REOM was set. At thattime the flip-flop 471 is set and its output is gated to digital device18 on line EOMR by AND gate 472 when counter 469 overflows. Flip-flops473 and 474 are used to turn off the normal operation of data receivebuffer 450 and to put it into testing mode. The operation in that modewill be described below.

When JK flip-flop 468 is in the set state data receive buffer 450 isoutputting data to digital device 18 on eight lines 455 and when thatflip-flop is in the reset state data receive buffer 450 is reading datafrom data multiplexer 58 on eight lines MDI.

While flip-flop 468 is in the reset state, counter 469 is incremented aseach byte strobe occurs. The byte strobe is input to one-shotmultivibrator 477 which delays it until the byte has been read intomemory 466 and then applies it through inverter 475A to NOR gate 475.The output of NOR gate 475, which is applied to NOR gate 476, will risewhen flip-flop 468 is in the reset state and the output of multivibrator477 is high. When the flip-flop 468 is in the set state and digitaldevice 18 issues a command to falling edge trigger circuit 470, thestrobe output from that trigger circuit is also applied to NOR gate 476.The strobe output and the output of NOR gate 475 are ORed together inNOR gate 476 and applied to the count input of six-bit counter 469. Thecounter is assembled so that, when a pulse occurs on the count input,the counter is incremented by 1 and when a pulse occurs on the loadinput from NOR gate 462 through AND gate 462A, the five most significantbits of the data currently on input lines RBL are copied into the fiveleast significant bits of counter 469 and the most significant bit ofthe counter is cleared. The overflow (OVR) output of counter 469corresponds to the most significant bit of the six bits and the carryoutput of the counter occurs when the least significant five bits areall 1 and therefore a carry is about to occur from the fifth bitposition. The address input for memory unit 466 comprises the leastsignificant five bits of counter 469.

The outputs of memory 466 on eight lines 455 are the contents of thecell currently being addressed by counter 469. The contents of the celladdressed by counter 469 are set equal to the data on the eight linesMDI when a pulse is received on the write input, provided that theMemory Write is not inhibited. The inhibit incurs when counter 469 OVRis set. As already indicated, the output of NOR gate 475 provides apulse when a byte strobe occurs during the time that flip-flop 468 isreset. This pulse is gated by NAND gate 478 and the output of gate 478is used to drive the write input to memory 466. Gate 478 inhibits thewrite pulse if flip-flop 473 is set, which occurs in the testing mode asdescribed below.

DATA TRANSMIT BUFFER

FIG. 7D is a logic diagram of data transmit buffer 451 shown in FIG. 7A.The primary function of this unit is to collect thirty-two words of datafrom digital device 18 on eight lines 456 and transmit them to datamultiplexer 58 on eight lines SDO. This function is performed under thecontrol of JK flip-flop 481.

Flip-flop 481 is set by a pulse on the SCLEAR line from interfacecomputer 62 and is reset by a pulse appearing on the XMT line. Whenflip-flop 481 is in the set state, commands issued by digital device 18on the WT CMD line to rising edge trigger circuit 482 cause data to bewritten into memory 480. When flip-flop 481 is in the reset state, thethirty-two words stored in memory 480 are transferred to datamultiplexer 58 on lines SDO.

An address must be supplied to memory 480 for each word that is eitherwritten into or read out of the memory. These addresses are generated asfollows.

A pulse on line XMT is supplied by interface computer 62 when it wishesto initiate transmission of data out of memory 480 to data multiplexer58. Interface computer 62 supplies a pulse on line SCLEAR when the datacurrently in memory 480 has been transmitted and memory 480 can befilled with other data from digital device 18. The pulses appearing oneither of lines XMT or SCLEAR are applied through NOR gate 494 to thereset input of six-bit counter 483. This serves to initialize counter483 so that a zero address is applied to memory 480 when digital device18 begins to write a new set of thirty-two words and when the thirty-twowords currently contained in memory 480 are about to be transmitted todata multiplexer 58. When a pulse is applied to the count input ofcounter 483, its current value is incremented; and when the currentvalue is equal to or greater than thirty-two, it generates a signal onits OVR output.

A pulse is applied to the count input of counter 483 in two differentways. If data is currently being collected from digital device 18,flip-flop 481 is in the set state and a strobe is generated by risingedge trigger circuit 482, one for each write command issued by digitaldevice 18 on the WT CMD line. Thus NOR gate 486 generates an output tothe count input of counter 483 each time rising edge trigger circuit 482generates a strobe output. If flip-flop 481 is in the reset state,indicating that data is being transmitted to data multiplexer 58, theneach signal generated on line BS by data multiplexer 58 will causeone-shot multivibrator 484 to generate an output signal which is appliedto NOR gate 485 through inverter 485A. Thus each byte strobe will causeNOR gate 485 to generate an output which will pass through NOR gate 486to the count input of counter 483. Hence it can be seen that whendigital device 18 is writing into memory 480 the address at whichwriting occurs is governed by counter 483 which is incremented each timedigital device 18 issues a write command. When information is being readout of memory 480 to data multiplexer 58, counter 483 is incrementedeach time data multiplexer 58 sends out a byte strobe. The leastsignificant five bits of the output from counter 483 are made availableto interface computer 62 by means of the eight lines SBL, and the samefive bits are used as the address input to memory 480. It should benoted that the least significant five bits of the output of counter 483appear as the most significant five bits of eight lines SBL.

In addition to supplying the proper address on the address input ofmemory 480, it is necessary when writing into the memory to provide astrobe signal on the write input. The necessary signal it provided bythe strobe output of rising edge trigger circuit 482 which passesthrough NOR gate 487 unless NOR gate 488 is generating an output. Gate488 will generate an output and thus inhibit write signals from gate 487when data transmit buffer 451 is in the test state. This will occur whenflip-flop 489 is in its set state.

A signal on the write input of memory 480 will have no effect if asignal is present on the inhibit input of memory 480. This inhibitoccurs when counter 483 generates an overflow signal. When digitaldevice 18 has issued thirty-two consecutive write commands, the overflowoutput OVR of counter 483 will be set and thus inhibit memory 480 frombeing written into again. The overflow output signal from counter 483 isalso applied to the inhibit input of rising edge trigger circuit 482which prevents an acknowledgement signal from being sent to the digitaldevice 18 on the WT STS line.

Interface computer 62 monitors counter 483 by means of line SSUM, in themanner to be described hereinbelow, and causes the assembled data inmemory 480 to be transmitted to data multiplexer 58 when the memory isfull. Alternatively, digital device 18 can cause transmission of lessthan thirty-two words of data by providing a signal on line SEOM. When awrite command is issued on line WT CMD to rising edge trigger circuit482 by digital device 18, the resulting strobe output serves to clockD-type flip-flop 490 which then samples the line SEOM from digitaldevice 18. If a signal is present on this line, the output fromflip-flop 490 will inhibit rising edge trigger circuit 482 and also beavailable on line EOMS to interface computer 62, thus allowing interfacecomputer 62 to begin the transmission of the data in memory 480 to datamultiplexer 58.

Considering then the manner in which data from memory 480 is transferredto data multiplexer 58, this process is seen from FIG. 7D to beinitiated by a pulse on the XMT line from interface computer 62 toflip-flop 481. If this signal is issued during time period D₃, databytes will be transmitted to data multiplexer 58 in the subsequent timeperiods D₄ through D₃₅. At the same time a sixteen-bit checksum will becomputed by checksum circuit 491 and this sum will be transmitted overlines 457 during time periods D₃₆ and D₃₇. Checksum circuit 491 is thesame as checksum circuit 467 shown in FIG. 7C. This result isaccomplished using select circuit 492 which is the same circuit ascircuit 179 shown in FIG. 5B. The clock input to checksum circuit 491 ispulsed once for every incoming byte strobe by the output ofmultivibrator 484. The output of checksum circuit 491, which appears online 495, is set to 0 whenever an XMT pulse is applied to flip-flop 481.During time periods D₃ through D₃₅, the OVR output of counter 483 isreset and select circuit 492 will transfer the output from memory 480 onto the output lines SDO. In time periods D₃₆ and D₃₇ the OVR output ofcounter 483 is set and select circuit 492 will transfer the output ofchecksum circuit 491 on to the data output lines SDO.

It is advantageous for control computer 30 to be able to test theoperation of data receive buffer 450 shown in FIG. 7C and a datatransmit buffer 451 shown in FIG. 7D. This is accomplished by theprovision of special circuitry which assembles an incoming data packetfrom data multiplexer 58 in data receive buffer 450, transfers theassembled data to data transmit buffer 451, and subsequently transfersit back to data multiplexer 58. This entire operation takes placewithout requiring any interaction with digital device 18.

Referring then to FIG. 7C, it is understood that the application of apulse on the RCV line to flip-flop 468 causes an incoming data packet tobe stored in memory 466 in the manner described above. When thirty-twobytes of data have thus been stored, a pulse on line RTEST will setflip-flop 473 and thereby cause NAND gate 478 to inhibit further writepulses to memory unit 466. The data will remain in memory 466 until suchtime as it can be transferred to memory 480 in data transmit buffer 451shown in FIG. 7D.

The transfer of the data from memory 466 to memory 480 is effected bythe simultaneous application of pulses on line XMT to flip-flop 481 andon line STEST to flip-flop 489 of data transmit buffer 451, shown inFIG. 7D. The effect of the STEST pulse is to set flip-flop 489 andthrough inverter 489A and AND gate 462A load counter 469 in data receivebuffer 450. When flip-flop 489 is set incoming byte strobes frommultivibrator 484 are steered into the write input of memory 480 bymeans of NOR gates 488 and 487 and inverter 485A. Since an XMT pulse isissued simultaneously with the STEST pulse, counter 483 is reset and aseach of the next thirty-two byte strobes occur, the write input tomemory 480 is strobed and counter 483 incremented. While flip-flop 489is set, data select circuit 493 will steer data on line RDO from theoutput of memory unit 466 in data receive buffer 450 into memory 480.When thirty-two bytes of data have been transferred from memory 466 tomemory 480 test mode flip-flops 473 and 489 will be returned to theirnormal reset state. Flip-flop 489 is reset by the OVR output of counter483 when it overflows. Flip-flop 473 is reset by the next pulse on lineRCV.

CHANNEL SELECT CIRCUIT

Channel select circuit 452 shown in FIG. 7A is shown in more detail inFIG. 7E. This circuit allows digital device 18 to transfer an eight-bitchannel number on eight lines 458 through to interface computer 62 oneight lines SBC. The circuit operates as follows.

The channel number on line 458 is stored in eight-bit register 500. Theeight outputs from register 500 are clocked onto lines SBC by the strobeoutput of rising edge trigger circuit 501. The strobe output isgenerated when the digital device 18 sends a select command on line SLCMD to rising edge trigger circuit 501. Thus the eight-bit channelnumber on lines 458 is stored in register 500 when the select command isgenerated. Since the strobe output of rising edge trigger circuit 501 isapplied to the J input of JK flip-flop 502, and since the Q output of JKflip-flop 502 is connected to the inhibit input of rising edge triggercircuit 501, trigger 501 is inhibited immediately following the SL CMDsignal.

The Q output of flip-flop 502 is made available on line SELEC tointerface computer 62. When interface computer 62 detects that flip-flop502 is set, it reads the eight-bit channel number from register 500 onlines SBC and generates a signal on line SLCT to the K input offlip-flop 502. This resets flip-flop 502, thereby removing the inhibitfrom rising edge trigger circuit 501. This allows trigger circuit 501 toreturn an acknowledgement over line SL STS to digital device 18 which isthen free to issue another select command on line SL CMD.

There is a logical interlock between the channel select circuit 452, thedata receive buffer 450, and data transmit buffer 451 which insures thatno data is transmitted or received while the channel number is beingchanged by interface computer 62. This operates as follows.

When a channel select command has been issued and flip-flop 502 set,operation of data receive buffer 450 and data transmit buffer 451 bydigital device 18 is disabled. This is brought about by feeding the Qoutput of flip-flop 502 into the inhibit inputs of trigger circuits 470and 482 on the line labeled "SELECTED." Digital device 18 is alsoprevented from issuing the SL CMD signal to channel select circuit 452when memory 466 in data receive buffer 450 has been partially emptied.This effect is obtained by means of JK flip-flop 474 in data receivebuffer 450. That flip-flop is reset whenever an RCLEAR or RCV pulse isissued to flip-flop 468 or when the OVR output of counter 469 is set.Flip-flop 474 is set whenever digital device 18 issues an RD CMD signalto falling edge trigger circuit 470 which in turn issues a strobe to theJ input of JK flip-flop 474. By connecting the Q output of flip-flop 474to the inhibit input of rising edge trigger circuit 501 in channelselect unit 452 on the line labeled "BLOCK," select commands issued bydigital device 18 to rising edge trigger circuit 501 are disabled.

CHANNEL BREAK CIRCUIT

The channel break circuit 453 shown in FIG. 7A appears in greater detailin FIG. 7F. This unit transfers an eight-bit channel number over linesRCH from interface computer 62 to digital device 18.

Interface computer 62 issues a channel break command (BREAK) in order toprovide digital device 18 with an eight-bit channel number wheninformation transmission is to begin on a different channel than the onecurrently in use. This is accomplished by setting D-type flip-flop 510by means of a pulse on the BREAK input line. The Q output of flip-flop510 is connected to the inhibit input of falling edge trigger circuit511 so that when flip-flop 510 is set the trigger circuit is enabledallowing digital device 18 to issue a command on line BK CMD to fallingedge trigger circuit 11. An indication that such a command can be issuedis provided by status line BK STS which is set when falling edge triggercircuit 511 is enabled and is reset after a command has been issued. Thestrobe output of falling edge trigger circuit 511 is connected to theclear input of flip-flop 510 so that when a command has been issued thatflip-flop is reset and falling edge trigger circuit 511 is inhibited.Interface computer 62 detects that digital device 18 has issued acommand on line BK CMD by examining line BK EKO which is connected tothe Q output of flip-flop 510.

INTERFACE COMPUTER

Interface computer 62, which is shown in FIG. 2B to be part of terminalinterface unit 17, is shown in block diagram form in FIG. 9A. Interfacecomputer 62 is a small digital computer which has a single eight-bitaccumulator 602, sixteen eight-bit words of working storage 604, and 256sixteen-bit words of read-only program store 600. This computersupervises and controls transmission activity by means of control linesthat connect at the various parts of the transmission equipment as hasbeen shown in the preceding FIGS. These control lines are organized sothat they appear to interface computer 62 to be seven storage words,each containing eight bits. These control lines are known collectivelyas the "peripheral store" and are shown as peripheral store 611 in FIG.9A.

The instruction repertoire for interface computer 62 is given below inTable I. As shown in FIG. 8, each instruction word of interface computer62 contains sixteen bits which are organized into an operation codefield of two bits, a T field of one bit, an R field of five bits, and anX field of eight bits.

                  TABLE I                                                         ______________________________________                                        Instruction Repertoire for the Terminal Interface                             Computer                                                                      ______________________________________                                        CONTROL INSTRUCTIONS                                                                  Operation                                                             Mnemonic                                                                              Code      T      R     Instruction                                    Form    Field     Field  Field Definition                                     ______________________________________                                        GOTOa   00        0      00000 Unconditional jump                                                            to the program                                                                store location                                                                specified by a                                 BTa     01        0      00000 Jump to the program                                                           store location                                                                specified by a if a =                                                         0                                              BFa     10        0      00000 Jump to the program                                                           store location                                                                specified by a if a                                                           ≠ 0                                      WAIT    11        0      00000 Wait for Byte strobe                           GOTOx   00        1      00000 Unconditional jump                                                            to the program                                                                store location                                                                specified by x                                 BTx     01        1      00000 Jump to the program                                                           store location                                                                specified by x if a =                                                         0                                              BFx     10        1      00000 Jump to the program                                                           store location                                                                specified by x if a                                                           ≠ 0                                      WAIT    11        1      00000 Wait for Byte strobe                           ______________________________________                                        ARITHMETIC AND LOGICAL INSTRUCTIONS                                                   Operation                                                                     Code     T       Instruction                                                  Field    Field   Definition                                           ______________________________________                                        A= a!r  00       0       Form the logical EXCLUSIVE                                                    OR of a and the contents of the                                               specified by r and store the                                                  result in A                                          A= a    01       0       Form the logical AND of a and                                                 the contents of the specified by                                              r and store the result in A                          A= a+ r 10       0       Add a to the contents of the                                                  location specified by r and store                                             the result in A                                      A= a→ r                                                                        11       0       Store a in the location specified                                             by r and also in A                                   A= x!r  00       1       Form the logical EXCLUSIVE                                                    OR of x and the contents of the                                               location specified by r and store                                             the result in A                                      A= x & r                                                                              01       1       Form the logical AND of x and                                                 the contents of the location                                                  specified by r and store the                                                  result in A                                          A= x+ r 10       1       Add x to the contents of the                                                  location specified by r and store                                             the result in A                                      A= x→ r                                                                        11       1       Store x in the location specified                                             by r and in A                                        ______________________________________                                    

Referring to Table I, the instruction repertoire is seen to comprisecontrol instructions and arithmetic and logical instructions. Controlinstructions are characterized in that the R field is 0. If the T fieldis a 0 then, as shown in Table I, the accumulator, A, contains theoperand for the instruction. If the T field is a 1 then the operand forthe instruction is the contents of the X field. Note that in Table I thevarious instruction word fields are denoted by upper case letters whilethe contents of the fields are denoted by lower case letters.

The arithmetic and logical instructions are seen in Table I to includeaddition, the logical AND, and the logical EXCLUSIVE OR functions. Inthe arithmetic and logical instructions, as in the control instructions,a 1 value in the T field indicates that one of the operands, x, iscontained in the X field while a 0 l in the T field indicates that oneof the operands is contained in the accumulator, A. The other operand ineach case is found at the location specified by r, the contents of the Rfield.

The locations which can be specified by the R field are shown in TableII to include the sixteen working storage locations denoted by W_(i),where 0≦i≦15, the seven peripheral store locations V_(k), where 0≦k≦6,and the accumulator.

                  TABLE II                                                        ______________________________________                                        R Field Formats                                                               R                Location                                                     Field (Binary Value)                                                                           Specified                                                    ______________________________________                                        10000 + i        Working storage location                                                      W.sub.i, where 0 ≦ i ≦ 15.                     01000 + k        Peripheral interface                                                          word V.sub.k, where 0 ≦ k ≦ 6.                 01111            Accumulator.                                                 00000            No location, this                                                             specifies that the                                                            instruction is a                                                              control instruction.                                         ______________________________________                                    

Referring again to FIG. 9A, it can be seen that program store 600,outputs sixteen bit instruction words to instruction register 601. Theoutput from instruction register 601 and the output from accumulator 602are gated by means of selection circuit 608 onto eight lines 609. Fromlines 609 the information may be transferred into program counter 605,which controls the addressing of program store 600, into eight-bitfunction generator 603, into peripheral store 611, or into working store604. Gating into the peripheral store is controlled by write selectcircuit 607.

Function generator 603 provides the means for performing the functionsof addition, logical AND, EXCLUSIVE OR, and an additional function inwhich, upon command, the data on lines 609 are merely transferred to thefunction generator 603 output which comprises accumulator 602. Functiongenerator 603 also supplies a special status signal whenever its outputis 0. This status signal is gated into flip-flop 606. Function generator603 obtains one of its inputs from the eight lines 609 and the other isobtained from eight lines 610. Data on lines 609 is obtained either frominstruction register 601 or from accumulator 602 depending upon theoperation of select circuit 608. The data on lines 610 may be fromworking store 604 or from either accumulator 602 or peripheral store 611as determined by gating circuit 619. The function of the interfacecomputer may best be appreciated by a consideration of the manner inwhich the instructions in Table I above are executed.

Each cycle of interface computer 62 may be conveniently divied into foursections which are shown as t₁, t₂, t₃, and t₄ in the timing diagram ofFIG. 9B. During time interval t₁, a sixteen-bit instruction is read outof program store 600 into instruction register 601. The outputs from themost significant eight bits of the instruction register then determinethe behavior of the machine during the remaining three time periods inthe machine's cycle. This behavior is different for each of the eightdifferent instructions described in Table I. For all instruction types,the machine increments the program counter 605 at time t₂. The output ofthis counter, at the subsequent time t₁ selects the instruction to beused for the following machine cycle.

First consider the eight control instructions. The instructions are seento comprise two groups, the first having a T-field of 0, as indicated inTable I, and the second having a T-field equal to 1. The value of Tdetermines the behavior of selection circuit 608. If T equals 0,selection circuit 608 allows the output of accumulator 602 to pass ontobus 609. If the T-field is a 1, selection circuit 608 allows the leastsignificant eight bits of the current instruction contained in the Iregister 601 to pass onto bus 609.

The operation code field in the instruction determines what use is madeof the value that is gated onto bus 609. In a "GOTO" instruction thecontents of bus 609 are loaded unconditionally into the program counter605 during the time period starting at t₂. This action overrides thepreviously mentioned operation of adding 1 to the program counter. Theresult of this action is, of course, that the next instruction is takenfrom the address specified by the value on bus 609.

The instruction whose operation code field has the value 01 is a jumpinstruction that is conditional on the value in accumulator 602. Theeffect of that instruction is to transfer the contents of bus 609 intothe program counter 605 if the accumulator contains 0. The instructionwith operation code 10 has the effect of transferring the contents ofbus 609 into the program counter 605 if the contents of the accumulator602 is non-zero. It is possible to determine whether the contents of theaccumulator is 0 by examining flip-flop 606. If the set output offlip-flop 606 is 0, then the contents of accumulator 602 are zero.

In either of the two conditional jump instructions, if the jump isactually to take place and information is to be transferred from bus 609into program counter 605, this operation takes place starting in thetime period beginning at t₂ and overrides the previously mentioned actof incrementing the program counter.

The remaining control instruction has operation code 11 and is a WAITinstruction which stops the operation of the interface computer. Theinterface computer will resume operation when it receives a byte stobesignal from the data multiplexer 58.

The eight arithmetic and logical instruction listed in Table I can alsobe grouped into two sets of four instructions. In one set the T-field isa 1, in the other it is a 0. As with the previously described controlinstructions, the T-field governs the action of selection circuit 608.

The operation code of the instruction in register 601 determines whatvalue is to be computed in the function generator and subsequentlystored in the accumulator 602. The computed value is stored in theaccumulator at time t₁, that is, at the beginning of the nextinstruction cycle. At the same time, flip-flop 606 is set either to 0 orto 1 as the result put into the accumulator is 0 or non-zero. Foroperation code 11 the value stored in the accumulator is equal to thevalue on bus 609. For operation code 10 the value stored in theaccumulator is equal to the sum of the value on bus 609 and the value onthe bus 610. For operation code 01 the value stored in the accumulatoris the logical AND of the value on bus 609 and the value on bus 610. Foroperation code 00 the value stored in the accumulator is the EXCLUSIVEOR of the value on bus 609 and the value on bus 610.

Operation code 11 has the additional effect of storing the value frombus 609 into one eight-bit register, either in the working store 604 orin the peripheral store 611. The particular register concerned isdetermined by the R field of the instruction currently in theinstruction register 601. That field also determines the contents of bus610 which is equal to the contents of one of the words either from theworking store 604 or the peripheral interface 605, or possibly from theaccumulator 602. If a store instruction takes place, that is, if theoperation code is 11, then it takes place at time t₃.

Interface computer 62 shown in block diagram form in FIG. 9A is shown ingreater detail in FIGS. 9C through 9G. Referring then to FIG. 9C,program store 600 shown therein comprises a 256-word-by-sixteen-bitread-only memory unit. This memory may be formed, for example, from fourintegrated circuits of type SN74187 manufactured by Texas Instruments,Inc.

The output of program store 600 comprises sixteen-bit words which areclocked into instruction register 601 when clock signal C1 is applied toinstruction register 601. The outputs of instruction register 601, whichhave been labeled in FIG. 9C in accordance with the instruction wordformat shown in FIG. 8, are applied to the remainder of the interfacecomputer circuitry as shown to provide the requisite control signals.

The clock signals used by the interface computer are supplied by theclock circuit shown in FIG. 9G. Astable multivibrator 650 shown in FIG.9G supplies a train of pulses to the clock input of D-type flip-flop651. Flip-flop 651 transfers these pulses on to flip-flop 652 if the Dinput to flip-flop 651 is not inhibited by NOR gate 666. The Q output offlip-flop 652 is applied to AND gate 653, the output of which comprisesthe C1 clock signal used in FIGS. 9C, 9D and 9E. The Q output offlip-flop 652 forms the C2 clock signal and is also applied to AND gate654, the output of which is the C4 clock signal. The clock signals thussupplied by the output of flip-flop 652 are phased as shown in FIG. 9B.

NOR gate 666 and flip-flops 655 provide the means for stopping thegeneration of clock signals when a WAIT signal occurs. This signal issupplied by AND gate 669 shown in FIG. 9C. The inputs to AND gate 669are supplied by AND gate 668 and NOR gate 612. As can be seen from FIG.9C, AND gate 668 generates an output when both bits in the operationcode field of the word currently in instruction register 601 are 1. NORgate 612 generates an output when the first two bits in the R field ofthe word currently in instruction register 601 are 0. Referring back toTable 1, it thus can be seen that the WAIT signal is generated whenevera WAIT instruction is present in instruction register 601.

Returning then to FIG. 9G, it is seen that when the WAIT signal isapplied to flip-flop 655 it causes the Q output to rise at the next C4pulse. This inhibits NOR gate 666 which causes the Q output of flip-flop651 to remain a 1, thereby enabling AND gates 653 and 654. Since the Qoutput of flip-flop 651 remains a 0, no further pulses are supplied tothe clock input of flip-flop 652, causing this flip-flop to remain inthe state where its Q output is a 1 and its Q output is a 0. The clockcircuit thus halts with the C1 output a 1 and the C2 and C4 outputs a 0.The point of the clock signal waveforms at which the clock circuit haltsis graphically shown in FIG. 9B by the line labelled "HALT." The clockcircuit resumes normal operation when flip-flop 655 is reset by the bytestrobe from data multiplexer 58 on line BS. Since a 0 is required toreset a D-type flip-flop, the byte strobesignal must be inverted byinverter 667.

Returning then to FIG. 9D, it is seen that the outputs of instructionregister 601 corresponding to the X field of an instruction word areapplied to select circuit 608 which operates in the same manner asselect circuit 179 shown in FIG. 5B. The select input to select circuit608 is the one-bit T field output from instruction register 601 whichservs to gate onto eight lines 609 the X field from instruction register601 if T=1, and the contents of eight-bit accumulator 602 if T=0.

The clocking of accumulator 602 shown in FIG. 9E is performed by the CAsignal from AND gate 645 which is generated by each C1 clock signalunless inhibited by the Q output of flip-flop 613 being a 0. The Qoutput of flip-flop 613 is a 0 only when the value gated into its Dinput by the C4 pulse is a 1. This only occurs during a controlinstruction at which time both inputs to NOR gate 612 are 0 therebycausing its output to be a 1.

The input to eight-bit accumulator 602 is supplied by eight-bit functiongenerator 603 which computes the aforementioned four functions from thetwo eight-bit operands on lines 609 and 610. Function generator 603 canbe made from two four-bit function circuits of type 74181 manufacturedby Texas Instruments, Inc. The two-bit operation code available frominstruction register 601 must be suitably gated to provide the propersignals to the S₀, S₁, S₂, S₃ and M inputs of the type 74181 functioncircuits. The gating that is required is shown in Table III.

                  TABLE III                                                       ______________________________________                                        0.sub.1  0.sub.2                                                                             S.sub.0   S.sub.1                                                                           S.sub.2 S.sub.3                                                                           M                                    ______________________________________                                        0        o     1         0   0       1   1                                    0        1     0         1   1       1   1                                    1        0     1         0   0       1   0                                    1        1     1         1   1       1   0                                    ______________________________________                                    

This gating is accomplished by the voltage -V, NAND gate 614, andinverter 615 as shown in FIG. 9E.

If the four bit result from each of the two function circuits is zero,then their "C" outputs are each 1. These outputs are combined by NANDgate 616 to yield a signal that is 0 if the result stored in accumulator602 is non-zero and are applied to zero detector 606 shown in FIG. 9Cwhich is seen to comprise a D-type flip-flop that is clocked by the CAsignal from AND gate 645.

The outputs of flip-flop 606 and NOR gate 612 are combined by AND-NORgate 617 with the two operation code bits as inverted by inverters 670and 671 to determine whether a control instruction is currently residentin instruction register 601. The AND-NOR gate 617 may be obtained, forexample, as part number 74H55 manufactured by Texas Instruments, Inc.The output of AND-NOR gate 617 is a 0 if a control transfer is presentand it causes eight-bit program counter 605 to be loaded by the datacurrently on bus 609. The count input of program counter 605 is providedby the C2 pulse and its output drives the address leads of program store600.

The other storage unit used by interface computer 62 is working store604 shown in FIG. 9E. This storage unit contains sixteen eight-bitstorage locations. These locations have been previously referred to inTable II as locations W_(i), where 0≦i≦15. The W_(i) are used to storethe information required by that part of the communication process thatis executed by the interface computer. In the detailed explanation ofthis process which is to follow hereinafter, the W_(i) are, forconvenience referred to by mnemonic designations. These are given inTable IV below along with an explanation of the contents of eachlocation.

                  TABLE IV                                                        ______________________________________                                        Working                                                                       Store                                                                         Location                                                                              Mnemonic   Explanation                                                ______________________________________                                        W0      SOUT       Status of the signal output routine                        W1      DOUT       Status of the data output routine                          W2      DIN        Status of the data input routine                           W3      DERR       List of errors detected by the data                                           input routine                                              W4      SSEQ       Sequence number of the last                                                   packet transmitted by the data                                                output routine                                             W5      LIMIT      Sequence number of the last                                                   packet that the data output                                                   routine is allowed to transmit                             W6      RSEQ       Sequence number of the packet                                                 which the data input routine                                                  next expects to receive                                    W7      SELCH      Channel number that is currently                                              selected for data output from                                                 the digital device                                         W8      FOUT       The information which is to be                                                inserted in byte S.sub.1 of the next                                          signal packet to be transmitted                                               by the signal output routine                               W9      NOUT       The information which is to be                                                inserted in byte S.sub.2 of the next                                          signal packet to be transmitted                                               by the signal output routine                               W10     FIN        The information that was in byte                                              S.sub.1 of the last signal packet that                                        was received by the signal input                                              routine                                                    W11     NIN        The information that was in byte                                              S.sub.2 of the last signal packet that                                        was received by the signal input                                              routine                                                    W12     COUT       The information which is to be                                                inserted in byte D.sub.1 of the next                                          data packet to be transmitted                                                 by the data output routine                                 W13     LOUT       The information which is to be                                                inserted in byte D.sub.2 of the next                                          data packet to be transmitted                                                 by the data output routine                                 W14     CIN        The information that was in byte                                              D.sub.1 of the last data packet that                                          was received by the data input                                                routine                                                    W15     LIN        The information that was in byte                                              D.sub.2 of the last data packet that                                          was received by the data input                                                routine                                                    ______________________________________                                    

Working store 604 may be constructed from a pair ofsixteen-word-by-four-bit integrated circuit memories such as bipolar LSImemory 3101 manufactured by Intel, Inc. The four-bit address required toaccess working store 604 is obtained from the least significant fourbits, R₁, R₂, R₃ and R₄, of the R field of the instruction currently ininstruction register 601. Working store 604 is selected if the mostsignificant bit, R₀, of the R field is 1. Input in working store 604occurs during time t₂ shown in FIG. 9B from eight lines 609 when asignal is supplied by AND gate 618 to the write input of the store.Output from working store 604 is available on eight lines 610 when a 1is present on the select input of the store.

The major remaining portion of the interface computer is peripheralstore 611 shown in FIG. 9D. As previously mentioned, peripheral store611 actually comprises a plurality of sets of input and output lineswhich are treated by interface computer 62 like a series of memorylocations. These input and output lines provide the means for the flowof commands and data between interface computer 62 and the rest of theterminal interface unit 17. Table V below provides a list of these inputand output lines and an explanation of their functions.

                  TABLE V                                                         ______________________________________                                        Peri-  Line                                                                   pheral Name                                                                   Store  in FIGS. 9C,                                                                              Function                                                   Location                                                                             9D, and 9E  Performed                                                  ______________________________________                                        Pheripheral Store                                                             Output Lines                                                                  V.sub.6                                                                              MDO         These eight lines transfer a byte of                                          control information to shift                                                  register 251 of data multiplexer                                              58 shown in FIG. 6A                                        V.sub.5                                                                              RCH         These eight lines transfer to                                                 digital device 18 the channel                                                 number on which data is                                                       currently available                                        V.sub.4                                                                              RBL         These five lines transfer to                                                  counter 469 shown in FIG. 7C                                                  the length of the data in the                                                 data packet currently being                                                   input to data receive buffer                                                  450. These five lines                                                         correspond to the five most                                                   significant bits of eight-bit                                                 register 630                                               V.sub.2                                                                              CMDB        This comprises the seven lines:                                   XMT         This line transmits the pulse that                                            causes data transmit buffer 451                                               shown in FIG. 7D to transfer                                                  data to data multiplexer 58.                                      SCLEAR      This line transmits the pulse that                                            causes data transmit buffer 451                                               shown in FIG. 7D to allow the                                                 digital device 18 to write into                                               data transmit buffer memory                                                   480                                                               RCV         This line transmits the pulse that                                            causes data receive buffer 450                                                shown in FIG. 7C to receive                                                   data from data multiplexer 58                                     RCLEAR      This line transmits the pulse that                                            causes data receive buffer 450                                                shown in FIG. 7C to allow the                                                 digital device to read from data                                              receive buffer memory 466                                         BREAK       This line transmits the pulse that                                            causes the channel break                                                      circuit 453 shown in FIG. 7F to                                               send the BK STS signal to                                                     digital device 18 thereby                                                     informing it that there is a                                                  channel number waiting                                            REOM        This line transmits the pulse that                                            causes data receiver buffer 450                                               shown in FIG. 7C to send an                                                   end of message, EOMR, signal                                                  to digital device 18                                              SLCT        This line transmits the pulse that                                            causes channel select circuit                                                 452 shown in FIG. 7E to read a                                                channel number from digital                                                   device 18                                                  V.sub.0                                                                              CMDA        This comprises the five lines:                                    RTEST       This line transmits the pulse that                                            puts data receive buffer 450                                                  shown in FIG. 7C into the test                                                mode                                                              STEST       This line transmits the pulse that                                            puts data transmit buffer 451                                                 shown in FIG. 7D into the test                                                mode                                                              SENDS       This line transmits a pulse that                                              informs data multiplexer 58                                                   that the terminal interface unit                                              17 wants to send a signal packet                                  SENDD       This line transmits a pulse that                                              informs data multiplexer 58                                                   that the terminal interface unit                                              17 wants to send a data packet                                    ALIVE       This line transmits a pulse to AND                                            gate 73 shown in FIG. 2B that                                                 enables power monitor 76 to                                                   keep protection relay 54 closed                            Peripheral Store                                                              Input Lines                                                                   V.sub.6                                                                              MDI         The eight lines transfer a byte of                                            information from data                                                         multiplexer 58 to receive buffer                                              memory 466 of data receive                                                    buffer 450 shown in FIG. 7C                                                   and also to the interface                                                     computer 62 shown in FIG. 9D                               V.sub.4                                                                              SBC         These eight lines transfer the                                                channel number selected by                                                    digital device 18 from register                                               500 of channel select circuit                                                 452 shown in FIG. 7E                                       V.sub.3                                                                              SBL         These five lines are the most                                                 significant of the eight lines 623                                            shown in FIG. 9D. They                                                        transfer from counter 483                                                     shown in FIG. 7D the length of                                                the data in the data packet                                                   currently stored in the data                                                  transmit buffer 451. These five                                               lines correspond to the five                                                  least significant bits of six-bit                                             counter 483                                                V.sub.2                                                                              STSB        This comprises five lines:                                        SSUM        This line transmits a pulse from                                              counter 483 of data transmit                                                  buffer 451 shown in FIG. 7D                                                   when the counter overflows                                        RSUM        This line transmits a pulse from                                              counter 469 of data receive                                                   buffer 450 shown in FIG. 7C                                                   when the counter overflows                                        SELEC       This line transmits a pulse from                                              channel select circuit 452                                                    shown in FIG. 7E that indicates                                               that the digital device 18 has                                                provided another channel                                                      number                                                            BKEKO       This line transmits a pulse from                                              channel break circuit 453                                                     shown in FIG. 7F. The pulse                                                   ends when the digital device 18                                               has acknowledged the channel                                                  number previously sent by the                                                 interface computer 62                                             EOMS        This line transmits a pulse from                                              data transmit buffer 451 shown                                                in FIG. 7D that indicates that                                                digital device 18 has sent an                                                 end-of-message signal to data                                                 transmit buffer 451                                        V.sub.1                                                                              TID         These eight lines transfer the                                                terminals identification number                                               from patch block 381 of data                                                  multiplexer 58 shown in FIG.                                                  6B                                                         V.sub.0                                                                              STSA        This comprises seven lines:                                       BPER        This line transmits a pulse from                                              data multiplexer 58 shown in                                                  FIG. 6E when a bipolar error is                                               detected in the packet just                                                   received by the data                                                          multiplexer                                                       ERROR       This line transmits a pulse from                                              data receive buffer 450 shown                                                 in FIG. 7C when an error is                                                   detected in a data packet                                         D.sub.36    This line transmits a pulse from                                              data multiplexer 58 when it                                                   transmits the 36th byte of a                                                  data packet                                                       FRAMEOUT    This line transmits a pulse from                                              data multiplexer 58 when it                                                   detects a T1 framing error                                        SEND        This line transmits a pulse from                                              data multiplexer 58 when it is                                                transmitting a new packet                                         READ        This line transmits a pulse from                                              data multiplexer 58 when it is                                                reading a signal or data packet                                               having the terminals'                                                         identification number                                             PKT         This line transmits a timing signal                                           pulse from data multiplexer 58                             ______________________________________                                    

Considering first the input lines 620 through 626 of peripheral store611 (FIG. 9D). These and lines 627 from a register 602 are seen to begated onto eight lines 610 by gating circuit 619 shown in FIG. 9D.Gating circuit 619 comprises eight gates 619A-619H. Each of these eightgates has eight input bit positions. Each of the eight incoming cables620 through 627 comprises eight wires. One wire from each of these eightcables is connected to a particular input bit position on each of eightgates 619A-619H. Gates 619A-619H each output that input bit positionselected by the three-bit address R₂, R₃, R₄. Since the same three-bitaddress is always supplied to each of eight gates 619A-619H, each of theeight gates always outputs the same input bit position. Thus, eachthree-bit address supplied to gating circuit 619 results in the gatingof each of the eight wires of one of cables 620 through 627 onto theeight output lines 610. Gates 619A-619H supply an output whenever the R₀bit connected to their inhibit inputs is a zero. These gates may eachcomprise integrated circuits of the type 8231 manufactured by Signetics,Inc.

Considering next the output lines 640 through 644 of peripheral store611, these are seen to be supplied from the eight-bit registers 628through 632 shown in FIG. 9D. These registers are set by the signals oneight lines 609 under the control of write select circuit 607. Writeselect circuit 607, which may comprise part number 74874 manufactured byTexas Instruments, selects which of five registers 628 through 632 is toreceive an input from lines 609 at any given time. This selection ismade in accordance with the three least significant bits of the R fieldif it is not inhibited by a signal from NAND gate 634 (FIG. 9C). NANDgate 634 uses the O₀, O₁, R₁ and R₀ as inverted by inverter 634A togenerate an inhibit at all times except when a transfer is to be made toperipheral store 611. Registers 628 through 630 each comprise eightD-type flip-flops. The clock inputs for each of these registers areprovided by NOR gates 635 through 637, respectively, each of whichserves to combine the C4 clock signal and the appropriate output fromwrite select circuit 607. Registers 631 and 632 also each comprise eightD-type flip-flops, 631A-631H and 632A-632H, respectively. The eightreset inputs to each flip-flop in each of these two registers is theinverted byte strobe signal on line BS as inverted by inverter 674. Theeight flip-flops 631A-631H of register 631 each take their preset inputfrom one of the eight NAND gates 638A through 638H which make up gate638. Each of NAND gates 638A-638H has three inputs: the C4 signal, oneof eight lines 609, and the output of inverter 672. Similarly, the eightflip-flops 632A-632H of register 632 each take their preset input fromone of the eight NAND gates 639A through 639H which make up gate 639.Each of NAND gates 639A-639H has three inputs: the C4 signal, one ofeight lines 609, and the output of inverter 673.

THE COMMUNICATION PROCESS

The apparatus described above provides the transmission paths by whichthe digital data transmission system of this invention actuallytransmits and receives data. As briefly discussed in conjunction withFIG. 1B, this apparatus is controlled by stored programs in interfacecomputer 62 and control computer 30. The method by which this control isachieved will now be discussed in greater detail.

FIG. 10A is a functional diagram of the data and signals that aretransmitted on a full-duplex basis between a switching unit 10 and adigital device 18 through a terminal interface unit 17.

As shown in FIG. 10A a digital device 18 issues a channel select commandto its associated terminal interface unit (TIU) 17 each time it wishesto begin a new transmission of data. TIU 17 then sends an SEL signal tothe switching unit 10 which replies with an ACK signal. Datatransmission then proceeds. As bytes of data are sent from digitaldevice 18 to TIU 17, they are accumulated into data packets and thensent to switching unit 10, which periodically acknowledges them with anACK signal.

In the other direction, switching unit 10 sends an SEL signal to the TIU17 when it has accumulated a quantity of data for the digital device 18.TIU 17 then sets the channel break status line thereby informing digitaldevice 18 that there is data ready for it. When digital device 18 hasselected the appropriate channel, switching unit 10 delivers the datapackets to TIU 17 which transfers the data in bytes to digital device 18and periodically sends an ACK signal to switching unit 10 inacknowledgment.

FIG. 10B is a functional diagram of the data and signals that aretransmitted on a full-duplex basis between two switching units 10. Thistransmission is exactly the same on both halves of the full-duplex path.

As shown in FIG. 10B, when data is about to be transmitted fromswitching unit 10a, that unit sends an STRT signal to switching unit10b, which acknowledges it with an ACK signal. Data transmission thenproceeds. As data becomes available in switching unit 10a it is sent inpackets to switching unit 10b, which periodically acknowledges this bysending an ACK signal. Certain errors may be detected by switching unit10b in which case NACK signals are sent to switching unit 10a. Finally,when switching unit 10a ceases to transmit data it sends an IDL signalto switching unit 10b.

The data and signal transfers shown functionally in FIGS. 10A and 10Bcan best be appreciated through an understanding of the data formatsshown in FIGS. 11A, 11B and 11C.

FIG. 11A shows a signal packet and a data packet. As shown, a signalpacket comprises four eight-bit bytes.

Considering first the signal packet, it is seen that its first byte,byte 1100, contains an identification number (ID). Since the mostsignificant bit of ID is used to specify the direction of data transfer,the ID provides the capability of multiplexing up to 128 TIU's on eachof the transmission loops 14 shown in FIG. 1A. In this case the IDserves to uniquely identify each TIU. Since the same data format is usedon transmission lines 12 that serve to interconnect pairs of switchingunits 10, each such transmission line 12 is effectively multiplexed into128 full-duplex transmission paths. These are termed "trunks" andcomprise a system resource which is allocated and assigned in the mannerto be explained hereinbelow. Of course, an ID of different size, therebyallow the capability of multiplexing a different number of TIU's andtrunks, may be used without departing from the spirit and scope of theinvention.

Byte 1101, shown in greater detail in FIG. 11B, comprises a six-bitsequence number 1112 and a two-bit F field 1113. Sequence numbers areconsecutively applied to both SEL signal packets and data packets duringtransmission on loop 14 and are consecutively applied to date packetsduring transmission on line 12. The significance of the SEQ field 1112as well as the CH byte 1102 depends upon the value of the F field 1113.

The F field 1113, if zero, indicates that the packet is an acknowledge(ACK) packet. The SEQ field 1112 is used to acknowledge the receipt ofdata of SEL signals and contains the sequence number applied to the lastdata packet or SEL signal correctly received. The significant of the CHfield 1102 in an acknowledge packet depends upon the circumstances inwhich the packet is being used. When the ACK signal is issued by aswitching unit to either a TIU or other switching unit, the CH field1102 serves to authorize further transmissions. In that case, the CHfield 1102 contains the last sequence number that can be used forsubsequent transmission. When the ACK signal is issued by a TIU the CHfield 1102 contains zero if no transmission errors have been detected,and contains the appropriate error codes as listed below in Table VI iferrors have been detected.

                  TABLE VI                                                        ______________________________________                                        Value           Error                                                         ______________________________________                                        1               Framing trouble                                               2               Control checksum error                                        4               Wrong channel                                                 8               Wrong sequence number                                         16              Bipolar format error                                          32              Data checksum error                                           ______________________________________                                    

The F field 1113, if a one, indicates an SEL signal when used on a loop14 and indicates an STRT signal when used on a line 12. In an SELsignal, the SEQ field 1112 is a sequence number, as described above, andthe CH byte 1102 contains the number of the selected channel. In an STRTsignal, the two fields 1112 and 1102 are combined to form a 14 bitnumber identifying the channel on which communication is about to start.

The Field 1113, if a two, indicates an IDL signal and the SEQ field 1112is the last sequence number used in the immediately prior transmission.

The Field 1113, if a three, indicates an NACK signal and the SEQ and CHfields 1112 and 1102, respectively, are used in the same manner as in anACK signal from the TIU.

Finally, byte 1103, the last byte in the signal packet, contains an 8bit checksum which is generated by program means and which comprises theEXCLUSIVE OR of the value contained in fields 1100, 1101, and 1102.

The data packet shown in FIG. 11A also includes an eight-bit byte 1104which contains the ID number of the packet. Byte 1105, shown in greaterdetail in FIG. 11C, comprises a six-bit sequence number 1110 and atwo-bit type field 1111. If field 1111 contains the value two, then thedata packet is an end-of-message packet. If field 1111 contains thevalue one, then the data packet is an end-of-bundle packet. If field1111 contains zero, then the data packet merely contains data and isneither an end-of-message nor and end-of-bundle packet.

Byte 1106 of the data packet contains the length L, of the data in thepacket. A length of zero, by convention, indicates a full packet of 32bytes. If the packet is less than full, the information must be in theleading part of the 32-byte field and the remaining positions cancontain any value.

Byte 1107 of the data packet contains an eight-bit program-generatedchecksum.

Field 1108 contains the actual data and may be up to 32 eight-bit bytesin length. Finally, field 1109 contains a sixteen-bit hardware-generatedchecksum.

The method by which the aforementioned α and β processes use thesignalling capability illustrated by FIGS. 10A and 10B can best beappreciated by referring again to FIG. 1B. Each channel such as the oneillustrated in FIG. 1B comprises two subchannels, each subchannel beingconcerned with data transmission in one direction. The description whichfollows shall be directed to the algorithm that handles datatransmission on one subchannel, subchannel 15 shown in FIG. 1B, and itis understood that data transmission on a full channel is achievedthrough the application of the algorithm twice.

It will be remembered that there are two sets of parameters and twoprocesses involved in the transmission on one subchannel. The α processor algorithm controls outgoing data and updates the α parameters of thesubchannel. The β process or algorithm controls incoming data andupdates the β parameters of the sub-channel.

The detailed process of this invention is based upon certain importanttechniques which will now be discussed before proceeding to a detaileddescription of the algorithms.

Digital data is transmitted in accordance with this invention in bursts,where a "burst" is defined as that data which is transmitted by adigital device during one continuous period of activity on one channel.A burst starts with an SEL signal and ends with either the next SELsignal or a data packet with an end-of-message code in it. Systemresources are assigned for the purpose of transmitting one burst andreassigned for subsequent bursts. "System resources" are here understoodto mean data packet storage space in a switching unit and trunks on atransmission line that interconnects two switching units.

Each link of a channel in the data transmission from one switching unitto another can use at most one trunk, and therefore no one channel canabsorb all available trunks. However, there is a danger that one channelmight use all the storage in one or more switching units. Therefore, thefollowing constraints are used.

Storage space in a switching data is assigned in units data M packets,where "M" is a parameter that is a constant for each channel. Theparticular value given to M for a specific channel is determined whenthe channel data virtually allocated. When burst transmission begins,the β process obtains the assignment of M storage locations, data alltransmission there have been loaded by the β process with data it hasreceived, it requests another assignment of M storage locations. datadata packet must be used.

DATA

The storage locations by the β process are then made available to theassociated α process for retransmission. When the retransmission issatisfactorily completed, the α process releases the storage locations.They are then available for assignment to the next β process that makesa request for storage allocation. Hence the amount of storage, denotedby "V," in a switching unit which is actually assigned to an activesubchannel is the sum of all those assignments of M made to thesubchannels β process less the amount of storage released by thesubchannel's α process.

The V assigned to a particular subchannel is constrained not to begreater than a particular value "A," where "A" is another constant thatis specified for the subchannel. Hence so long as A-V<M for a particularsubchannel, the requests for further allocation of storage by thatsubchannel's β process will not be honored. This use of the ACK signalsprovides the means whereby the data transmission system of thisinvention automatically matches the transmitting speed of each sendingdigital device to the receiving speed of each digital device to which ittransmits.

The manner in which the data transmission system of this inventioncontrols the transfer of data is dependent upon all data being assignedsequence numbers which are used by the ACK signals both to acknowledgecorrect receipt of the data which has been thus far transmitted and toauthorize further transmission. The use of a six-bit sequence number, ashas been done in this exemplary embodiment, allows a single ACK signalto authorize transmission of at most 63 data packets. Alternativeembodiments could, of course, use a sequence number of different size toallow the authorizatin of transmission of a greater or lesser number ofpackets without departing from the spirit and scope of this invention.

The packets transmitted between successive authorization signals arecollectively referred to as a "bundle." Since this embodiment uses asix-bit sequence number it will be appreciated that the size of a bundlemay not be greater than 63 packets. In fact, it may comprise less thanthis number, the length being determined by the α process whichtransmits it. The maximum authorization that a β process will send isdetermined by the parameter N, which is a constant for the subchannel.Thus N is a second constrain on the maximum size of a bundle. In allcases, the last packet in a bundle is uniquely identified by type field1111 shown in FIG. 11C. By convention, an SEL signal is always the endof a bundle. A digital device may arbitrarily divide the data it sendsto another digital device into units termed "messages." When a sendingdigital device transfers the last byte of a message to its associatedTIU, it must set the SEOM line as previously discussed in conjunctionwith FIG. 7D. By convention, the last packet of a message defines theend of a bundle and the end of a burst.

The operation of the α and β algorithms can be understood with referenceto FIG. 1B by considering the transfer of data from TIU 19 to switchingunit 21 through switching unit 20.

As shown in FIG. 1B, the α_(T1) process of terminal interface unit 19 isconnected to the β_(T1) process of switching unit 20. The other half ofthe switching unit 20 portion of subchannel 15 is the α_(T2) processwhich connects to the β_(T2) process of switching unit 21.

Consider first a transmission from α_(T1) to β_(T1). Data and SEL signalpackets passing from α_(T1) to β_(T1) are sequence numbered as describedabove and these sequence numbers are checked by β_(T1). Only data andSEL signal packets which have consecutive numbers are accepted forprocessing by β_(T1), all others are treated as errors. When the digitaldevice associated with TIU 19 desires to start transmission onsubchannel 15, it must issue a select for that channel which will thenresult in an SEL signal being sent by α_(T1) to β_(T1). Upon arrival atβ_(T1) that SEL signal will constitute a request for resources for thetransmission of one burst of data from α_(T1) through switching unit 20onto link 25. In particular, β_(T1) makes a request for a subtrunk toimplement link 25 and for storage space in switching unit 20sufficiently large to accommodate M packets of data. If either of thesetwo resources cannot currently be assigned to β_(T1), then transmssionto switching unit 20 on subchannel 15 is suspended until sufficientresources become available.

One the requested resources have been assigned to β_(T1), the SEL signalfrom α_(T1) is acknowledged by sending an ACK signal from β_(T1) toα_(T1) authorized the start of data transmission. The α_(T1) processwill, if the digital device provides enough data, send the authorizednumber of packets of data to β_(T1), marking the last of these packetsas the last of a bundle. As each packet is received, β_(T2) checks itssequence number and stores it in switching unit 20. When the last packetof the bundle is received, β_(T1) wil construct a new ACK signal andsend it to α_(T1). That new ACK signal confirms the successul receptionof the transmitted data and authorizing transmission of more data untilthe total amount transmitted is equal to M. When this occurs, β_(T1)will request storage space for another M packet of data. When thisrequest is honored, β_(T1) again sends an ACK signal to α_(T1).

When β_(T1) receives either an SEL signal or the last packet of amessage, thus signifying the end of a burst, any unused storageresources assigned during burst transmission but currently unused forstorage of data are returned to the common storage pool in switchingunit 20.

Considering next the transmission from α_(T2) to β_(T2), it is apparentthat this depends upon β_(T1) supplying to α_(T2) the data received fromα_(T1). β_(T1) makes this data available to αT₂ by placing it in afirst-in-first-out queue which can also be accessed by α_(T2). α_(T2)constantly tries to empty the queue by retransmitting the data toβ_(T2). The transmission process comprising sequence numbering of thedata packets and use of the ACK signal to authorize further transmissionthat was described above is also used to effect this retransmission.

Although the process for transmission of data on link 25 shown in FIG.1B is the same as that previously described for link 24, the signallingassociated with the start and end of a burst is different.

A burst on link 25 starts when the β_(T1) process obtains an assignmentof a subtrunk linking switching units 20 and 21. At that time an STRTsignal is sent over the assigned subtrunk to switching unit 21. Aspreviously mentioned, the SEQ and CH fields are combined to uniquelyspecify that portion of subchannel 15 passing through switching unit 21shown in FIG. 1B. When switching unit 21 receives the STRT signal itassociates the assigned subtrunk number with the proper sub-channel sothat subsequent transmissions on that subtrunk will be correctly handledby the β_(T2) process. The signal also causes β_(T2) to requestresources for burst transmission in the same way as was described abovefor β_(T1).

The end of a burst occurs when α_(T2) runs out of data to transmit andat the same time no burst is in progress on link 24. At that time α_(T2)releases the subtrunk which it has been using to implement link 25. Thesubtrunk then becomes available for reassignment. When the subtrunk isreleased, and periodically thereafter, switching unit 20 sends an IDLsignal over that subtrunk for as long as it remains unassigned. Ifswitching unit 21 receives an IDL signal on the subtrunk while it isassociated with β_(T2), then it disassociates that subtrunk from β_(T2)and informs β_(T2) that the burst is finished. At this time, the actionof β_(T2) is the same as that previously described for β_(T1) at thecompletion of a burst.

The communication process utilized by this invention in the manner setforth above is implemented by stored programs that reside in eachinterface computer 62 and each control computer 30 shown in FIG. 2B.Each interace computer executes the same program as every otherinterface computer in the system and each control computer executes thesame program as every other control computer in the system. The detailsof these two programs will now be discussed, considering first theinterface computer program and then the control computer program.

THE INTERFACE COMPUTER PROGRAM

FIGS. 12-16B are seen to comprise flow charts of the initializationinstructions and the four routines that correspond to the α and βprocesses as performed by the interface computer: the initializationinstructions shown in FIG. 12, the data output routine shown in FIGS.13A and 13B, the data input routine shown in FIGS. 14A and 14B, thesignal output routine shown in FIG. 15, and the signal input routineshown in FIGS. 16A and 16B. The data output routine implements the datahandling portion of the α process, while the data input routineimplements the data handling portion of the β process. The signal inputand output routines are used by both the α and β processes to performthe signaling that each requires.

Each of the four interface computer routines is functionally independentof the others. However, each contains sequences of instructions thatmust be performed in particular ones of the time periods which have beenset forth graphically in FIG. 7B, during which terminal buffer 60 cantransmit control information. The four routines contain instructionsthat must be executed during the D₃₇, S₀, S₁, S₂, S₃, D₀, D₁, D₂, andD₃, periods as well as some instructions, termed asynchronousinstructions, that may be executed between the D₃ and D₃₇ time periods.The execution of the instructions in the proper time sequence isachieved by interleaving the functionally independent portions of eachof the four routines according to the time periods in which they must beexecuted. For ease of description, each routine will be explainedindividually. The exact manner in which the instruction interleaving maybe performed is, however, set forth in the program listing of AppendixA, which is a list of the contents of program memory 600 of interfacecomputer 62 shown in FIG. 9A.

The flow charts of FIGS. 12-16B are seen to include several differentsymbols. A rectangle, termed up "operation block" is used to indicate anarithmetical or logical step in the process. A diamond, termed a"conditional branch point" indicate a decision step of the process. Anellipse, termed a "terminal indicator" delineates the various sequencetimes during which the instructions must be performed. A circle is usedmerely as a drafting aid to indicate the proper flow from one sheet ofthe drawing to another.

INITIALIZATION INSTRUCTIONS OF THE INTERFACE COMPUTER PROGRAM

Turning then to the flow charts, FIG. 12 illustrates the severalinitialization instructions which must precede the four interleavedroutines to insure that each cycle of execution begins at the start ofthe D₃₇ time period.

The flow chart of FIG. 12 has two entry points, 750 and 754. The STARTentry 750 is used to initialize the interface computer program.Operation block 751 begins this process by setting working storelocations SOUT, DOUT, DIN, SSEQ, RSEQ, and LIMIT to zero. Block 752 thensends an XMT command to the data transmit buffer 451 causing it toprevent the digital device 18 from writing data into the buffer. Nextblock 753 issues an RCV command to the data receive buffer 450 causingit to prevent any data from being read out of that buffer by the digitaldevice. Control then passes to operation block 755.

The RESTART entry 754 is used when it is required to disconnect the TIU17 from the transmission loop 14. To obtain this effect control ispassed to block 755, which sets SOUT equal to three and then passescontrol to the main loop of the interface computer program atconditional branch point 756.

Conditional branch point 756 tests whether data multiplexer 58 hasobtained frame synchronization with the transmission loop 14. That factis indicated by a 0 on line FRAMEOUT. If that line is a 1, indicatingthat frame synchronization has not been achieved, conditonal branchpoint 756 continues to loop back to block 755. If data multiplexer 58 isin synchronization with the transmission loop control passes fromconditional branch point 756 to conditional branch point 757.

The sequence comprising conditional branch point 757 and block 758maintains the connection of the TIU to the transmission loop 14 byappropriate pulsing of power monitor 76 shown in FIG. 2B which keeps theprotection relay 54 in the loop access module 16 closed for as long asthe value in working store location SOUT is not equal to three. If thevalue in working store location SOUT is equal to three, controltransfers from conditional branch point 757 around block 758 toconditional branch point 759. Otherwise, control passes to block 758. Inblock 758 an ALIVE command is issued to power monitor 76 which causesthe protection relay 54 to remain closed for the next time period ofabout 250 microseconds. The sequence comprising conditional branch point759 and operation block 760 causes interface computer 62 to wait fortime period D₃₆. During that time period the D36 input line is equalto 1. If that line is not equal to 1, then conditional branch point 759transfers control to block 760 and block 760 causes interface computer62 to wait for another byte strobe. Following the arrival of the nextbyte strobe, control passes back to conditional branch point 759. Ifconditional branch point 759 determines that input line D36 is equal toone, synchronization is now obtained with the time period D₃₆ andcontrol passes to block 761. Block 761 waits for the byte strobe toarrive signaling the start of time period D₃₇. This time period is thetime at which the first sequence of execution of the four main routinesis to begin and hence control passes from block 761 to these routines.This action is shown schematically in FIG. 12 as block 762. After theexecution of the asnychronous sequence of the last of these routines,control passes back to block 756 and the cyclic operation of theinterface computer program is repeated.

DATA OUTPUT ROUTINE OF THE INTERFACE COMPUTER PROGRAM

Turning then to FIGS. 13A and 13B, these are seen to comprise a flowchart of the data output routine. The function of the data outputroutine is to handle the output of a data packet and to supervise theoperation of data transmit buffer 451. This routine maintains thesequence number SSEQ discussed hereinbefore in Table IV. It stores thedata packet control data in COUT, the data packet length in LOUT, andthe process status in DOUT. The sequence number for the end of thecurrent bundle is held in LIMIT and SELCH contains the number of thecurrently selected output channel.

As shown in FIG. 13A, the first function performed by the data outputroutine takes place during the D₃₇ interval and comprises blocks 800through 805. The purpose of these blocks is to complete if necessary,the outputting of a data packet from data transmit buffer 451 to datamultiplexer 58. This operation may have been begun during the last cycleof the interface computer program and may not as yet have beencompleted. Conditional branch point 801 tests whether DOUT is equal tofour. As previously mentioned. Dout stores the status of the routine. Ifindeed the data output routine is in the process of outputting a databyte, then DOUT will equal four. If this is not the case, thenconditional branch point 801 will transfer control to the next sequence,the S₃ sequence which begins at block 806.

If DOUT does equal four, the conditional branch point 801 transferscontrol to conditional branch point 802 which tests the value of COUT.COUT corresponds to the TYPE field in the CNTRL byte of a data packet.Thus COUT takes the value two if the data packet is the end of a messageand therefore the end of a bundle, takes the value one if it is merelythe last packet in a bundle without being the last packet in a message,and takes the value zero if it is neither the last packet in a bundlenor in a message. If COUT is not equal to zero, thus indicating that thecurrent packet is either an end-of-bundle or end-of-message, then statusword DOUT is set equal to eight by block 803, which serves to indicatethat the data output routine is now waiting for an ACK signal. Controlis then transferred by block 803 to the the beginning of the S₃ sequenceat block 806.

If COUT is zero, then the current data packet is neither anend-of-bundle nor an end-of-message, and block 804 sends an SCLEARcommand to data transmit buffer 451. This will cause data transmitbuffer 451 to allow digital device 18 to write in another packet ofdata. Status word DOUT is then set equal to 1 by block 805 indicatingthat digital device 218 is now currently reading a new data packet intodata transmit buffer 451. At this point, control is transferred toterminal indicator 806 at which time the S₃ sequence is begun.

During time period S₂ the sequence starting at block 806 is obeyed. Thatsequence starts with conditional branch point 806 where a test is madeon DOUT. If DOUT is equal to two, it indicates that the data outputroutine is waiting to transmit a packet of data. If the data outputroutine is not so waiting, conditional branch point 807 transferscontrol to the D₀ sequence starting at operation block 809. If the dataoutput routine is waiting to transmit a data packet, then block 808issues a SENDD command to data multiplexer 58. This command causes themultiplexer to look for an opportunity to transmit a data packet.

The sequence starting at terminal indicator 809 is executed in timeperiod D₀. That sequence comprises only block 810 in which the contentsof working storage location COUT are transferred to data output linesMDO. The effect of this is to cause data multiplexer 58 to transmit asbyte D₁ of a data packet the value which is currently contained in COUT.

The sequence beginning at terminal indicator 811 is executed in timeperiod D₁. That sequence comprises block 812 in which the contents ofworking store location LOUT are transferred to data output lines MDO,causing data multiplexer 58 to write the value from LOUT into byte D₂ ofthe outgoing data packet. If the multiplexer is not currentlytransmitting, then blocks 810 and 812 will have no useful effect.

The sequence which begins at terminal indicator 812A is executed in timeperiod D₂. This sequence is in fact redundant and has no useful effectif data multiplexer 58 is not actually transmitting data; and if themultiplexer is transmitting, the effect of this sequence is to output inbyte D₃ of the outgoing data packet the checksum which is computed asthe EXCLUSIVE OR of the values in bytes D₀, D₁, and D₂ of a data packet.Block 813 computes this value using the fact that peripheral store linesTID carry the terminal ID which is written into byte D₀ of the datapacket and the fact that working store locations LOUT and COUT containthe values inserted in byte positions D₁ and D₂, respectively, of thatpacket. The result computed by block 813 is transferred to data outputlines MDO by block 814.

The sequence which starts at terminal indicator 815 is obeyed in timeperiod D₃. First, conditional branch point 816 tests the SEND line fromdata multiplexer 58. That line is equal to 1 if data multiplexer 58 isin fact transmitting a data packet. Conditional branch point 816transfers control to terminal indicator 820 if data multiplexer 58 isnot transmitting data. When the data multiplexer is transmitting data,SEND is 1 and conditional branch point 816 transfers control to block818 where an XMT command is issued to data transmit buffer 451. Theeffect of this command is to cause the buffer to transmit during timeperiods D₃ through D₃₆ the thirty-two bytes of data held in the buffer,followed by the sixteen-bit checksum which that buffer computes.Operation block 819 then sets DOUT equal to four, indicating thattransmission of data is in progress.

The asynchronous sequence which begins at terminal indicator 820 isobeyed sometime between time period D₃ and time period D₃₇. First inthat sequence, as shown in FIG. 13B, conditional branch point 821 testsDOUT. If DOUT is not equal to 1, control is transferred to the end ofthe data output routine at terminal indicator 835. When DOUT equals 1,this indicates that the digital device is able to transfer data intodata transmit buffer 451.

When digital device 18 has finished transferring data into data transmitbuffer 451 either SSUM or EOMS will be set equal to 1. Alternatively,digital device 18 may select a new channel, in which case SELEC will beequal to 1. If any of these conditions exists, then the sequencebeginning at block 823 is obeyed, otherwise conditional branch point 822transfers control to the end of the data output routine at terminalindicator 835.

The sequence beginning at block 823 first works on the assumption thatdigital device 18 has inserted data into data transmit buffer 451 andthat that data should then be transmitted as a data packet. Thisassumption is good unless digital device 18 selected a new channel whendata transmit buffer 451 was empty. This condition is tested byconditional branch points 832 and 833.

Block 823 computes the sequence number to be used in the data packetwhich will next be transmitted. Next, conditional branch points 824 and827 and operation blocks 825, 826, and 828 compute the type of the datapacket to be transmitted. If the sequence number of the packet held inSSEQ is equal to the limiting sequence number held in LIMIT, thenconditional branch point 824 transfers control to block 826 where thetype of the packet is provisionally set in COUT to be equal to 1. IfSSEQ is not equal to LIMIT, then conditional branch point 824 transferscontrol to block 825 wherein the type of the packet is provisionally setto 0 in working storage location COUT.

Conditional branch point 827 is then executed and tests input line EOMS.This line is 1 if digital device 18 has indicated that the data storedin data transmit buffer 451 is the last of a message. If EOMS is equalto 1, then conditional branch point 827 transfers control to block 828wherein the packet type two is stored in working storage location COUT.If EOMS is not equal to 1, then conditional branch point 827 transferscontrol around block 828 to block 829.

The information which will go into byte position D₁ of the data packetcontains the sequence number in its most significant six bits and thepacket type in its least significant two bits. This value is computed inblock 829 and stored in COUT. Since the sequence number is already inthe most significant six bits of SSEQ, and since the type is already inthe least significant two bits of COUT, block 829 merely adds thecontents of working store locations COUT and SSEQ and stores the valuein COUT.

The information which is transmitted in byte D₂ of the data packet isequal to the length of the data in that packet. That length is currentlyavailable on input lines SBL which come from data transmit buffer 451.Operation block 830 stores this length in working store location LOUT.DOUT is then set equal to two by block 831. This indicates that the dataoutput routine is now waiting for an opportunity to transmit.

Conditional branch points 832 and 833 then proceed to test whetherdigital device 18 in fact wrote any data into data transmit buffer 451.If it did, then either the data length on lines SBL will be nonzero orline SSUM will be set equal to 1. If either of these conditions exist,then conditional branch points 832 and 833 will transfer control to theend of the data output routine at terminal indicator 835. If neither ofthese conditions exists, then digital device 18 must have selected a newchannel without writing any data into data transmit buffer 451, and inthis case block 834 is used to set DOUT equal to zero, indicating thatthe data output routine is calling upon the signal output routine totransmit an SEL signal. After obeying block 834, control is transferredto the end of the data output routine at terminal indicator 835.

DATA INPUT ROUTINE OF THE INTERFACE COMPUTER PROGRAM

This routine handles the input of a data packet and supervises operationof the data receive buffer 450. The process maintains a sequence numberin RSEQ, stores the data packet control and length information in CINand LIN, respectively, and stores the process status in DIN. If anyerrors are detected during input the type of error is noted in DERR.

As shown in FIG. 14A, the routine starts at terminal indicator 840 witha sequence which is obeyed in time period D₃₇. First in that sequence isconditional branch point 841 where a test is made on DIN to see if it isequal to 1, indicating that data is currently being received from datamultiplexer 58 by data receive buffer 450. If DIN is not equal to one,conditional branch point 841 transfers control to the D₁ sequencebeginning at terminal indicator 851. Otherwise, control is passed toconditional branch point 842.

Conditional branch point 842 checks whether there was a bipolar error ora checksum error in the data received by data receive buffer 450. Itdoes this by checking to see if either of the input lines BPER or ERRORis equal to 1. If neither is equal to 1, then conditional branch point842 transfers control to block 848, otherwise it transfers control toconditional branch point 843. If line BPER is equal to 1 then a bipolarerror was detected by multiplexer 58 and conditional branch point 843transfers control to block 844, where the value sixteen is added toworking store location DERR. If no such error was detected, thenconditional branch point 843 transfers control to conditional branchpoint 845.

If data receive buffer 450 detects a checksum error in the incoming datapacket, then line ERROR will be set to 1 and conditional branch point845 will transfer control to block 846 where the value 128 is added toworking store location DERR. if no such error was detected thenconditional branch point 845 transfers control to block 847. In block847 DIN is set equal to four, which serves to indicate that the datainput routine is now waiting for the signal output routine to send anACK signal. Operation block 847 then passes control to the D₁ sequencebeginning at terminal indicator 851.

As mentioned above, conditional branch point 842 transfers control toblock 848 if no error is detected in the incoming data packet. Block 848then sets DIN equal to two, indicating the data input routine is nowwaiting for digital device 18 to read data from data receive buffer 450,and control is transferred to operation block 849. Operation block 849sets the lines RBL equal to the value currently stored in working storelocation LIN which value is currently minus one times the length of thedata in the data packet. Then block 850 issues an RCLEAR command to datareceive buffer 450 causing that buffer to make the data it holdsavailabe to digital device 18. Control is then transferred to the D₁sequence beginning at terminal indicator 851.

The D₁ sequence starts with conditional branch point 852 where a test ismade on DIN. If DIN is equal to 0, then the data input routine iswaiting to read a data packet and conditional branch point 852 transferscontrol to block 853, which transfers the data available on input linesMDI from data multiplexer 58 to working store location CIN. Otherwise,control passes around block 853 to terminal indicator 854.

The next sequence, starting at terminal indicator 854, is executed intime period D₂ and comprises operation block 855 which transfers thedata on data input lines MDI to working store location LIN.

The next sequence is the D₃ sequence which begins at terminal indicator856. The first action taken by this sequence is to test whether a datapacket destined for TIU 17, in which the data input routine is running,is in fact being read by data multiplexer 58. That test is made inconditional branch point 857 by checking to see whether line READ isequal to 1. If READ is not equal to 1, then control is transferred tothe beginning of the asynchronous sequence at terminal indicator 873shown in FIG. 14B. If a packet is being read by data multiplexer 58,then line READ will equal 1 and control is transferred to conditionalbranch point 858A where a test is made on DIN to see if the data inputroutine is in fact waiting for more data input as is the case when DINequals 0. If no input is expected, the control is transferred fromconditional branch point 858A to the end of the D₃ sequence, that is, toterminal indicator 873 shown in FIG. 14B. Otherwise, control passes toblock 858.

Working store location DERR is used by the data input routine toaccumulate values indicating errors that have been detected during theinput process. In block 858 DERR is initialized to zero. Following block858, conditional branch point 859 and block 860 together check thesequence number of the incoming packet against that expected by the datainput routine as stored in RSEQ. If that check fails and the sequencenumber of the incoming packet is a number different from that expected,then a error code of eight is set in DERR. Conditional branch point 859extracts the sequence number from the most significant six bits of CINwhere it is deposited by block 853 during the input process. Thisextraction uses "$FC" as a mask, where the symbol "$" indicates thehexadecimal number system and F and C are hexadecimal digits. Thus "$FC"is the hexadecimal representation of the decimal number 252.

Conditional branch point 859 compares the extracted sequence number withthe sequence number in the most significant six bits of working storelocation RSEQ. If the sequence numbers are equal, control passes fromconditional branch point 859 to conditional branch point 861. Otherwise,block 860 sets an error code in DERR.

Conditional branch point 861 and operation block 862 then check whetherthe data input packet just received relates to a channel different fromthe one selected for data output. Working store location RCH containsthe number of the channel that was selected for data input and workingstore location SELCH contains the channel number chosen by digitaldevice 18 for data output. At conditional branch point 861 these twovalues are compared, and if they are equal, control is transferred tooperation block 863. Otherwise control passes to operation block 862where the error code four is inserted in working store location DERR.

Byte D₃ of each data packet is a checksum whose value should be theEXCLUSIVE OR of bytes D₀, D₁, and D₂, which byte values are currentlyavailable to the data input routine on input lines TID, in workinglocation CIN, and in working location LIN, respectively Block 863 thuscomputes the EXCLUSIVE OR of these three values. Conditional branchpoint 864 compares the result with the value currently on data inputlines MDI. If equality is found, then control passes from conditionalbranch point 864 around operation block 865 to operation block 866.Otherwise block 865 is used to set the error code two in working storelocation DERR.

Next, block 866 shown in FIG. 14A extracts the type of the incoming datapacket from the value currently held in CIN. That type is in the leastsignificant two bits of CIN and the effect of block 866 is to mask outand return to CIN just the two-bit quantity which is the type of theincoming packet. Conditional branch point 867 then checks whether theincoming packet is of type two. If it is not, control is passed aroundblock 868 to block 869. Otherwise, block 868 is used to set the commandline REOM. Command line REOM is an input to data receive buffer 450which signals if that the incoming data packet is the last of a message.At this point in the data input routine working store location LINcontains the length of data actually contained in the packet. This valueis shown as being negated by block 869. Since interface computer 62 doesnot have a subtract instruction, the two's-complement negative of thevalue in LIN is obtained in two steps. First the EXCLUSIVE OR of thatvalue with the hexadecimal value $FF (255 decimal) is formed. Then oneis added to the result.

Operation block 870 transfers the contents of working store location LINto the lines RBL where it is made available to data receive buffer 450.Operation block 871 shown in FIG. 14B then issues an RCV command to datareceive buffer 450 which causes it to start reading data from datamultiplexer 58. This is a process which continues from time period D₄through to time period D₃₇. To indicate that this input process istaking place, operation block 872 sets working store location DIN equalto 1.

The asynchronous sequence starting at terminal indicator 873 is obeyedduring the interval from time period D₃ through time period D₃₇. In theasynchronous sequence, the data input routine first checks to seewhether data in data receive buffer 450 is currently available todigital device 18 and whether digital device 18 has in fact justfinished taking the last byte of data from data receive buffer 450. Ifthat is the case, then working store location DIN is equal to two andinput lines RSUM are equal to 1. If the first of these conditions is nottrue, then conditional branch point 874 transfers control to conditionalbranch point 876. If the second of these conditions is not true, thenconditional branch point 875 transfers control to conditional branchpoint 876. If both conditions are true, then conditional branch point875 transfers control to conditional branch point 878. Conditionalbranch point 876 determines whether a channel break has been sent todigital device 18. If a channel break has been sent to digital device 18then working store location DIN will contain the value eight andconditional branch point 876 transfers control to conditional branchpoint 877. Otherwise, control passes to the end of the data inputroutine at terminal indicator 882.

Conditional branch point 877 determines whether the channel break hasbeen accepted and acknowledged by digital device 18. If it has, inputline BKEKO will contain the value 0 and conditional branch point 877will transfer control to operation block 880. Otherwise control willpass to the end of the data input routine at terminal indicator 882. Inblock 880 the working store location DIN is set to four, indicating thatthe data input routine is waiting for the signal output routine to sendan ACK signal. Operation block 880 passes control to block 881.

It can be seen from the above that when digital device 18 has completedcollecting data from data receive buffer 450 control passes toconditional branch point 878. At that point, the data intput routinechecks to see whether the type of packet just given to digital device 18is equal to 0. Working store location CIN stores the packet type. If thetype is nonzero, it must either be the last packet of a bundle or thelast packet of a message, and in either of these cases control passesfrom conditional branch point 878 to operation block 880 where, as seenabove, working store location DIN is set equal to four to indicate thatthe data input routine is waiting for the signal output routine to sendan ACK signal. If the type of the packet is zero, then control passesfrom conditional branch point 878 to operation block 879 where workingstore location DIN is set equal to 0 indicating that the data inputroutine is waiting for another input packet. Operation block 879 thenpasses control to operation block 881.

The sequence number of the next packet to be accepted by the data inputroutine is contained in the most significant six bits of working storelocation RSEQ. Operation block 881 increases RSEQ by four and thentransfers control to the end of the data input routine at terminalindicator 882.

SIGNAL OUTPUT ROUTINE OF THE INTERFACE COMPUTER PROGRAM

The signal output routine is illustrated in FIG. 15. This routinehandles the output of a signal packet contained in working storagelocations FOUT and NOUT. The state of the signal output routine isindicated by the current value of SOUT.

As shown in FIG. 15, the signal output routine begins at terminalindicator 890 in time period D₃₇. The signal output routine first checkswhether SOUT is 1 to see if it is waiting to send a signal. Conditionalbranch point 891 transfers control around operation block 892 toterminal indicator 893 if SOUT is not equal to 1, and transfers controlto block 892 where an SENDS command is issued to data multiplexer 58 ifSOUT is equal to one. The SENDS command requests transmission of asignal packet at the next opportunity.

The S₀ sequence starting at terminal indicator 893 comprises block 894in which the information in storage location SOUT is transferred ontodata output lines MDO and made available to data multiplexer 58 whichwill insert it as the second byte of an outgoing signal packet.

The S₁ sequence beginning at terminal indicator 895 comprises operationblock 896 where information in storage location NOUT is transferred ontodata output lines MDO which take it to the multiplexer 58 where it isinserted into byte S₂ of an outgoing signal packet.

The S₂ sequence begins at terminal indicator 896A. First, operationblock 897 computes the checksum to be transmitted as byte S₃ of theoutgoing signal packet. That checksum is the EXCLUSIVE OR of the threepreceding bytes of the signal packet and these values are available,respectively, on input lines TIC, in working store location FOUT, and inworking store location NOUT. This checksum is output onto data outputlines MDO by block 898.

It may happen that operation block 892 requested the opportunity totransmit a signal packet and data multiplexer 58 did not find anopportunity to do so in the current master frame time. This condition istested in conditional branch point 899. If so, input line SEND is equalto zero 0 and the operation performed by blocks 894, 896, 897, and 898will have been in vain. If input line SEND is equal to 1 it indicatesthat data multiplexer 58 was able to transmit a signal packet and inthis case conditional branch point 899 transfers control to operationblock 900. If this is not the case, conditional branch point 899transfers control to terminal indicator 901. In operation block 900 SOUTis set equal to two, indicating that the signal output routine hasdisposed of any current requests to send a signal packet and isavailable to process a subsequent request.

The asynchronous sequence beginning at terminal indicator 901 is obeyedduring time period S₃ and D₃₇. If at this point SOUT contains the valuetwo, then the signal output routine is available to service a request totransmit signals and the signal output routine thus goes on to determinewhether such a request exists. Conditional brance point 902 transferscontrol to the end of the signal output routine at terminal indicator906 if the signal output routine is not available to send a signal, thatis, if SOUT is not equal to two. Otherwise, control is transferred toconditional branch point 903.

If it is able to service this request to send a signal, conditionalbranch point 903 tests to see if the data input process is requestingthat an ACK signal be sent. That fact is indicated by the value fourstored in DIN. If an ACK signal is requested, conditional branch point903 transfers control to block 907. Otherwise, control passs toconditional branch point 904.

In conditional branch point 904 the signal output routine checks to seeif the data output routine is requesting the transmission of an SELsignal, that is, if working store location DOUT is equal to 0. If such asignal is requested, control is transferred from conditional branchpoint 904 to operation block 910. Otherwise control passes to the end ofthe signal output routine at terminal indicator 906.

Blocks 907, 908, and 909 handle the output of an ACK signal on behalf ofthe data input routine. Byte S₁ of the ACK signal contains the sequencenumber of the last packet received by the data input routine, whichnumber is one less than the six-bit number held in the most significantsix bits of working store location RSEQ. The purpose of block 907 is tocompute the sequence number of the last received packet and store thevalue in FOUT for subsequent transmission by the signal output routine.Byte S₂ of the ACK signal contains the error indication currently storedin working store location DERR. In block 908 this value is transferredto working store location COUT for subsequent output by the signaloutput routine. Block 909 sets DIN equal to 0, indicating to the datainput routine that it should now be waiting for further data packetinput and then transfers control to operation block 920.

The sequence starting at block 910 handles the output of the SEL signalon behalf of the data output routine. The number of the selected channelis provided by digital device 18, and is stored in channel selectcircuit 452 from which it is available to interface computer 62 on linesSBC. Block 910 stores the number of this channel in working storelocation SELCH. That number is to appear in byte S₂ of an SEL signal andthus operation block 912 transfers the channel number from SELCH toworking store location COUT from which it is subsequently transmitted bythe signal output routine.

Byte S₁ of an SEL signal contains in its most significant six bits thesequence number which is one greater than the last sequence numbertransmitted. That number is available in the most significant six bitsof working store location SSEQ. A 1 is stored in the least significanttwo bits of byte S₁ of the SEL signal packet. Block 913 computes thevalue of byte S₁ for the SEL signal packet using the sequence numberheld in SSEQ and stores the result in working store location FOUT forsubsequent transmission by the signal output routine. In block 914 thesignal output routine sets DOUT equal to sixteen indicating to the dataoutput routine that it should now be waiting for the ACK signal to bereceived. Operation block 915 then issues an XMT command which insuresthat digital device 18 cannot write more data into data transmit buffer450. Conditional branch point 916 checks to see if DIN is equal to two,that is, to see if there is data currently available in data receivebuffer 450. If this is not the case, control passes to block 920,otherwise control passes to block 917.

Operation block 917 issues an RCV command to data receive buffer 450.This insures that data currently resident in data receive buffer 450 isno longer made available to digital device 18. Then in block 918 DIN isset to four to indicate to the data input routine that it must now sendan ACK signal. In block 919 working store location DERR is set to fourto indicate that the most recently received data packet was treated asbeing an error for the reason that it applies to a channel that is nolonger the one selected for data output. From block 919 control passesto block 920 where SOUT is set equal to 1 indicating that the signaloutput routine is now waiting to transmit another signal. From block920, control passes to the end of the signal output routine at terminalindicator 906.

SIGNAL INPUT ROUTINE OF THE INTERFACE COMPUTER PROGRAM

The signal input routine is illustrated in FIGS. 16A and 16B. Thisroutine stores the second and third bytes of each signal packet inworking store locations FIN and NIN, respectively.

The signal input routine starts with the S₁ sequence beginning atterminal indicator 930. During time period S₁, block 931 copies the dataavailable on data input lines MDIN into woking store location FIN.

The S₂ sequence beginning at terminal indicator 932 is executed next.During time period S₂, block 933 transfers the data on data input linesMDIN into working store location NIN.

The next sequence executed by the signal input routine is the S₃sequence beginning at terminal indicator 934. Conditional branch point935 tests to see if a signal is in fact being read. This is indicated bythe READ input line. If that line is equal to 0, then no signal packetis in fact being read and conditional branch point 935 causes a transferto the end of the signal input routine at terminal indicator 943 shownin FIG. 16B. Otherwise control passes to conditional branch point 936.At this time the input line BPER is equal to one if a bipolar error wasdetected by data multiplexer 58 during the reading of the signal packet.Conditional branch point 936 transfers control to the end of the signalinput routine at terminal indicator 943 shown in FIG. 16B if an error isso detected, and if no error is detected, control passes to block 937.

Byte S₃ of a signal packet contains a checksum which is the EXCLUSIVE ORof the preceding three bytes, S₀, S₁, and S₂. At this point the valuesof these bytes are available on lines TID, in working store locationFIN, and in working store location NIN, respectively. Block 937 computesthe EXCLUSIVE OR of these three values, and conditional branch point 938compares that with the value available on data input lines MDIN. If thetwo values are found to be unequal, conditional branch point 938transfers control to the end of the signal input routine at terminalindicator 943 shown in FIG. 16B. Otherwise, control passes to block 939.The significance of the signal packet is determined by the function codein the least significant two bits of byte S₁ of the signal packet. Thatfunction code is extracted from the value stored in FIN by operationblock 939. Conditional branch points 940, 941, and 942 then transfercontrol to the sequence appropriate to the function value obtained.

Conditional branch point 940 transfers control to conditional branchpoint 944 if the function code of the incoming signal packet is 0indicating that it is an ACK signal. Otherwise, control is transferredto conditional branch point 941 shown in FIG. 16B. Conditional branchpoint 941 transfers control to conditional branch point 956 if thefunction code of the incoming signal packet is one, indicating that itis an SEL signal. Conditional branch point 942 shown in FIG. 16Btransfers control to conditional branch point 966 if the function codeof the incoming signal is two, indicating that it is an RST signal. Ifthe function code is not one of these values, then control passes t theend of the signal input routine at terminal indicator 943.

The sequence starting at conditional branch 944 shown in FIG. 16Ahandles the case when the incoming signal is an ACK signal. If the dataoutput routine is waiting for an ACK signal after transmitting the lastdata packet of a bundle, the value of DOUT is eight. A test of thisvalue is made by conditional branch point 944 and if that value isfound, control is transferred to block 948. Otherwise, it passes toconditional branch point 945.

If the data output routine has previously received an ACK signal whichindicated that it should not transmit any more data packets, the valueof DOUT is thirty-two. Conditional branch point 945 tests for this valueand, if it finds it, passes control to block 948. If not, control passesonto conditional branch point 946.

If the data output routine is waiting for an ACK signal after sending anSEL signal, then DOUT equals sixteen. Conditional branch point 946checks for this value. If the value sixteen is not found, control passesfrom conditional branch point 946 to the end of the signal input routineat terminal indicator 943 shown in FIG. 16B. If the value sixteen isfound, control passes to block 947. Block 947 sets DOUT equal to 0 as aprovisional measure indicating that if the incoming ACK signal has anincorrect sequence number, then the data output routine should requestthe signal output routine to send another SEL signal. Control thenpasses from block 947 to terminal indicator 949.

As mentioned above, block 948 is obeyed if either of the tests made byconditional branch points 944 and 945 are true. In this case, DOUT isset equal to two indicating to the data output routine that if theincoming ACK signal has an erroneous sequence number the data outputroutine should repeat the transmission of the most recently transmitteddata packet. Control then passes from block 948 to terminal indicator949.

In the D₀ sequence beginning at terminal indicator 949, the firstoperation is performed by conditional branch point 950 which comparesthe sequence number in the most significant six bits of working storelocation SSEQ with the sequence number from byte S₁ of the incomingsignal packet which is currently stored in working store location FIN.If these values are not equal, control passes through conditional branchpoint 950 to the end of the signal input routine at terminal indicator943 shown in FIG. 16B. Otherwise control passes to block 951. In block951 working store location LIMIT is set equal to the value stored inworking store location NIN.

The NIN value was obtained from the byte S₁ of the incoming signalpacket and is the sequence number of the last data packet which the dataoutput routine is authorized to transmit. If this value is equal to thevalue stored in SSEQ then the data output routine has transmitted allthat it is permitted to transmit and conditional branch point 952 passescontrol to block 955 where the working store location DOUT is set equalto thirty-two, indicating to the data output routine that it must waitfor another ACK signal. If working store location LIMIT is not equal toworking store location SSEQ, control passes from conditional branchpoint 952 to block 953 where an SCLEAR command is issued to datatransmit buffer 451 with the effect that digital device 18 is permittedto write more data into that buffer. Block 954 sets DOUT equal to one,indicating to the data output routine that digital device 18 is now ableto write into data transmit buffer 451. Control passes through blocks954 and 955 to the end of the signal input routine at terminal indicator943 shown in FIG. 16B.

The sequence starting at conditional branch point 956 shown in FIG. 16Bhandles the input of the SEL signal on behalf of the data input routine.Only if that routine is waiting for input will the SEL signal beaccepted. Thus conditional branch point 956 checks to see if workingstore location DIN is equal to 0, and, if it is not, passes control tothe end of the signal input routine at terminal indicator 943. Ifworking store location DIN is 0, block 957 is obeyed. In that block thesix-bit sequence number contained in the most significant six bits ofbyte S₁ of the incoming signal packet is extracted from working storelocation FIN. Conditional branch point 958 compares this sequence numberwith working store location RSEQ. If the two values are found to beequal, control passes to block 961. Otherwise control passes to block959.

Block 959 sets an error code of eight in working store location DERR andthen block 960 instructs the data input routine to request that thesignal output routine send an ACK signal. This it does by setting DIN tofour. After block 960, control passes to the end of the signal inputroutine, that is, to terminal indicator 943. In the case that controlpasses from conditional branch point 958 to block 961, the incoming SELsignal has been accepted and the channel number obtained from byte S₂ ofthe signal packet and currently stored in working store location NIN iscopied onto the lines RCH which are input lines to channel break circuit453.

Conditional branch point 962 compares the channel number now selectedfor data input and contained in working store location NIN with thechannel number selected for data output and currently contained inworking store location SELCH. If these values are equal, control passesto block 965. Otherwise, control passes to block 963. When these numbersare not equal, error code four is set in working store location DERR byblock 963 and a BREAK command is sent to channel break circuit 453 byblock 964. The effect of these actions is to make the number of thechannel selected for data input available to digital device 18.

After block 964 control passes to block 965 in which the signal inputroutine sets DIN equal to eight, indicating to the data input routinethat a new channel has been selected for data input. After this actionhas been taken, control passes to the end of the signal input routine atterminal indicator 943.

The sequence starting a conditional branch point 966 is obeyed if an RSTsignal is received. In that case, the value contained in byte S₂ of theincoming signal packet determines what further action should be taken.That value is currently stored in working store location NIN.Conditional branch point 966 transfers control to the RESTART entrypoint 754 of the signal input routine shown in FIG. 12 if the value inNIN is 0. Conditional branch point 967 transfers control to the STARTentry point 750 of the signal input routine shown in FIG. 12 if thevalue in working store location NIN equals 1. In the case that workingstore location NIN contains a value which is greater than 1, block 968is obeyed. In block 968 working store location SOUT is set equal to two.This action is significant if the previous value of SOUT was three,indicating that the terminal interface unit is disconnected from theloop access module by protection relay 54 shown in FIG. 2B. By settingSOUT to two, terminal interface unit 17 will attach itself to thetransmission line, an effect which is brought about by theinitialization instructions shown in FIG. 12. After block 968, controlpasses to the end of the signal input routine at terminal indicator 943.

THE CONTROL COMPUTER PROGRAM

The program that resides in the control computer 30 of each switchingunit 10 is a great deal more complex than the program that resides inthe interface computer 62 of each terminal interface unit 17. Eachswitching unit 10 may have a plurality of transmission lines 12 attachedto it as shown in FIG. 1A. Additionally, each switching unit 10 may havea plurality of transmission loops 14 attached to it as shown and each ofthese loops may interconnect through loop access module 16 up to 128 toterminal interface units 17. At any particular instant of time, thecontrol computer 30 of each switching unit 10 will therefore be handlinga large number of virtually allocated as well as actually assignedtransmission paths. This function is performed in accordance with theillustrative embodiment of this invention by a plurality of functionallydistinct routines and subroutines which are multiprogrammed by the TempoI computer which serves as control computer 30. In order to facilitatethe understanding of these routines and subroutines, the data structuresthat they use, which are illustrated in FIGS. 17-17L will first bediscussed.

The major components in the data structures are blocks of thirty-twosixteen-bit words. Each of these blocks is termed a "descriptor." Themanner in which the individual words of a descriptor are used dependsupon what it is that the particular descriptor describes. Each TIU 17shown in FIG. 1A has one descriptor which is stored in its associatedswitching unit 10. Each transmission loop 14 has one descriptor which isstored in its associated switching unit 10. Each transmission loop 14has one descriptor which is stored in its associated switching unit 10.Each transmission line 12 has two descriptors, one stored in each of thetwo switching units 10 which it serves to interconnect. Similarly, eachtrunk has two descriptors, one in each of the switching units 10 whichuse it. Each channel has one descriptor stored in each switching unit 10through which it passes. Finally, there is a single control unitdescriptor in each control computer that describes the switching unitwhich it contains.

Referring then to FIG. 17A, it is seen that all of the transmission loopdescriptors 1000, transmission line descriptors 1001 and control unitdescriptor 1002 contained in a single control computer 30 memory arelinked together by a circular pointer chain. Each pointer in this chainis contained in the NEXT field of each of these descriptors. For ease ofdiscussion hereinbelow loop descriptors 1000, line descriptors 1001, andcontrol unit descriptor 1002 are collectively referred to as "type 1"descriptors. A single storage location, LINE 1003, contains a pointer tothat descriptor currently being processed by control computer 30.

FIG. 17B shows a circular pointer chain of the TIU descriptors 1004 andtrunk descriptors 1005 that are contained in a single control computer30 memory. These descriptors are collectively referred to hereinbelow as"type 2" descriptors. The circular chain shown in FIG. 17B interconnectsall type 2 descriptors contained in control computer 30 by means of apointer in the NEXT field of each descriptor which points to the nextdescriptor in the chain. The single storage location SCANNED 1006contains a pointer to that one of the type 2 descriptors that was lastaccessed by the timeout routine in the manner to be describedhereinbelow.

FIG. 17C shows another pointer which is contained in line descriptor1001. This pointer, CHLIST, points to a chain of subchannel descriptors1007. There are two subchannel descriptors for each virtual channel thatis currently allocated in control computer 30. The pointer CHLIST shownin FIG. 17C points to a chain of the descriptors of those subchannelsthat are allocated to transmit data out of control computer 30 on aparticular transmission line 12. In that chain the NEXT field of eachsubchannel descriptor 1007 contains a pointer to the next subchanneldescriptor in the chain. The NEXT field of the last subchannel on thechain contains the value zero. The word CHLIST is zero if the chain isempty.

FIG. 17D shows another pointer which is contained in TIU descriptor1004. This pointer, CHANNELS, also points to a chain of subchanneldescriptors 1007. This chain comprises those subchannels which areallocated to transmit data to a TIU which is on a loop directlyconnected to the control computer 30. It can be seen in FIG. 17D thatthis chain is linked by the NEXT fields of subchannel descriptors 1007in the same way as those of FIG. 17C. Also, the word CHANNELS is zero ifthe chain is empty.

FIG. 17E shows another pointer which is contained in loop descriptor1000. This pointer TERMINALS, points to terminal index 1008 whichcontains pointers to TIU descriptors 1004. Although not shown in FIG.17E, each line descriptor 1001 also contains a pointer TERMINALS to aterminal index 1008. Each terminal index 1008 contains 128 entries, onefor each TIU ID if the terminal index 1008 is associated with a loopdescriptor 1000 and one for each trunk ID if the terminal index 1008 isassociated with a line descriptor 1001. The position of an entry in theterminal index 1008 corresponds to the ID of the type 2 descriptor towhich that entry points. For loop descriptors 1000, as shown in FIG.17E, the entries in the terminal index 1008 correspond to TIU IDnumbers.

As previously mentioned, a full-duplex channel is described as a pair ofsubchannels. FIG. 17F shows that the pair of subchannel descriptors1007A and 1007B for one channel comprise the channel descriptor 1009 forthe channel. The thirty-two word channel descriptor 1009 contains asixteen-word subchannel descriptor 1007A in its first sixteen words anda second sixteen-word subchannel descriptor 1007B in its second group ofsixteen words. The SINK fields in each subchannel descriptor 1007A and1007B contains pointers to the type 2 descriptors 1010A and 1010B,respectively, that correspond to the terminal interface units or trunksto which the subchannel is allocated for the transmission of data. Inthe case where a subchannel is allocated to transmit data to a trunk,the field SINK contains a pointer to a trunk descriptor 1005 only whilea trunk is actually assigned to that subchannel. When assignment of atrunk has not been made the field SINK of a sub-channel descriptorcontains zero.

FIG. 17F can be correlated to the illustrative channel shown in FIG. 1Bin the following manner. If channel descriptor 1009 shown in FIG. 17F isassumed to be associated with switching unit 20 shown in FIG. 20, thensubchannel descriptors 1007A and 1007B of FIG. 17F correspond to theβ.sub.τ1 /α.sub.τ2 and α_(Rn) /β_(R)(n-1) parameter pairs, respectively,and type 2 descriptors 1010A and 1010B correspond to the β.sub.τ2/α.sub.τ3 pair and β_(R) _(n) parameters, respectively.

Referring then to FIG. 17G, there can be seen another pointer of linedescriptor 1001. This pointer TRLIST, points to a chain of currentlyunassigned trunk descriptors 1005. TRLIST is zero if no trunk remainsunassigned and otherwise contains a pointer to the trunk descriptor 1005for the first unassigned trunk. Each trunk descriptor 1005 contains apointer, TRCHAIN, to the next trunk descriptor, 1005 in the chain, andthe TRCHAIN field of the last trunk descriptor on the chain containszero.

FIG. 17H shows a pointer, ATTNQ, which is contained in each type 1descriptor. ATTNQ points to data output attention queue 1011.

When a subchannel has data ready for output an entry is made in the dataoutput attention queue 1011 for the type 1 descriptor 1012 associatedwith the line onto which the data is to be transmitted. There is onequeue 1011 for each type 1 descriptor. In each 250 microsecond intervalone queue entry is processed. The position of the entry processed in themost recent interval is contained in the field DXLAST of the type 1dscriptor. An entry in the attention queue 1011 is either zero or apointer to a subchannel descriptor 1007 that has data ready for output.

FIG. 17I illustrated a signal output queue. Each signal output queueentry 1013 comprises four words. The entries 1013 are chained to form acircular chain by for of the NEXT fields. There is one signal outputqueue for each type 1 descriptor 1012. The fields SXTAIL and SXHEAD inthe type 1 descriptor 1012 contain pointers to queue entries 1013. Allthose queue entries 1013 in the circular chain starting at the entrypointed to by SXHEAD and terminating with the entry prior to the onepointed to by SXTAIL are the "active" queue entries. Each active queueentry specifies a signal that is to be sent out of the control computer.The field TMNL in each queue entry 1013 contains a pointer to the type 2descriptor 1010 for the terminal or trunk to which the signal is to bedirected. The fields FN and CH contain data to be used in constructingthe second and third bytes, respectively, of the signal packet.

As each data packet is received at control computer 30 it stored is in atwenty-one word storage area which is known as a "packet buffer" 1014.After certain checks have been completed, the packet buffer is placed ona queue of packet buffers where it waits for service. This queue isshown graphically in FIG. 17J. There is one such queue for eachtransmission line and each transmission loop. The type 1 descriptors1012 for each such transmission facility have fields DRHEAD and DRTAILthat contain pointers to the associated queue of packet buffers 1014.Field DRHEAD contains a pointer to the first packet buffer 1014 in thequeue and DRTAIL points to the last packet buffer 1014 in the queue.Each packet buffer 1014 contains a pointer, NEXT, to the next packetbuffer 1014 in the queue. The NEXT field of the last packet buffer 1014in the queue contains a pointer to the storage location that containsDRTAIL for the type 1 descriptor 1012. When the queue is empty, DRHEADcontains a pointer to the location DRTAIL.

FIG. 17K shows a typical signal input queue that is associated with onetype 1 descriptor 1012. Entries 1015 in that queue comprise four-wordunits which are formed into a circular chain by means of the NEXT fieldsin them. Each entry does not contain useful information at every instantof time. A pointer to the first that any particular time does containuseful information is stored in field SRHEAD of type 1 descriptor 1012.The queue entry 1015 pointed to by SRHEAD and successive entries on thecircular chain up to but not including the one pointed to from the fieldSRTAIL, all contain useful information that is waiting to be processed.That information is derived from signal packets received at controlcomputer 30. The field FN of a queuee entry 1015 contains a copy of thefirst two bytes from a signal packet, and the field CH contains a copyof the last two bytes from a signal packet. The TMNL field of queueentry 1015 contains a pointer to the type 2 descriptor 1010 to which thesignal packet relates.

After processing, data packets are stored in a data output queueassociated with the subchannel on which that data is being sent. FIG.17L shows a data output queue. There is one such queeue for eachsubchannel descriptor 1007. The queue comprises entries 1016 of fourwords each that are chained together in a circular chain by means of theNEXT field in each entry 1016. As seen in FIG. 17L the chain formed bypointers in the NEXT fields of the data output queue entries 1016 ismatched by a circular chain comprising pointers in the PREV fields ofeach entry 1016. The circular chain made from the PREV fields traversethe circle of queue entries in the reverse direction to that of the NEXTfields.

Three other pointers of interest appear in each subchannel descriptor1007 to which a data output queue relates. These pointers are in fieldsDATAQH, DATAQT and NEXTOUT. The queue entries 1016 that currentlycontain information to be processed occupy successive positions aroundthe circular chain starting with the particular entry 1016 that ispointed to by the field DATAQH and ending with the entry prior to theone pointed to by the field DATAQT. Data will have been transmitted fromsome of these queue entries 1016 but the entries remain in the dataoutput queue until acknowledgement of the transmission is received atthe control computer. A pointer to the first queue entry 1016 for whichdata has not been transmitted is contained in the field NEXTOUT. Thefield TYPE of each queue entry 1016 contains the value 2 if theassociated data packet is the last of a message, otherwise the value iszero. The field DBLK in each queue entry 1016 contains a pointer to thepacket buffer 1014 holding data to be transmitted.

In addition to these pointers, the data structures discussed inconjunction with FIGS. 17A-17L contain other pointers and data which areused by the program of control computer 30. In order to aid the detaileddescription of the various parts of this program, all of the datastructure entries are listed below in Table VII.

TABLE VII Type I Descriptor Fields

NEXT Pointer to next type 1 descriptor in a circular chain. Position inthe data output attention queue 1011 of the last entry processed.

SXHEAD Pointer to the first active signal output queue entry 1013.

SXTAIL Pointer to the signal output queue entry 1013 following the lastactive entry.

DRHEAD Pointer to the first packet buffer 1014 in the queue of bufferswaiting for input processing.

DRTAIL Pointer to the last packet buffer 1014 in the queue of bufferswaiting for input processing.

SRHEAD Pointer to the first active signal output queue entry 1015.

SRTAIL Pointer to the signal output queue entry 1015 following the lastactive entry.

TERMINALS Pointer to the terminal index 1008.

ATTNQ Pointer to the data output attention queue 1011.

DXMASK Contains one less than the length of the data output attentionqueue 1011. That length must be a power of two.

TRLIST Pointer to the first trunk descriptor 1005 for an unassignedtrunk.

CHLIST Pointer to the first sub-channel descriptor 1007 that has beenallocated to output data on line described by the type 1 descriptorcontaining this field.

TRUNKDEBT This contains minus one times the maximum number of channelswhich can be virtually allocated to output data on the transmissionline.

SIGCH Pointer to the sub-channel descriptor 1007 to be used for controlmessages on this transmission line.

CHLOW The lower bound on channel numbers that can be chosen by thecontrol computer for use on this transmission line.

CHHIGH The upper bound on the channel numbers that can be chosen by thecontrol computer for use on this transmission line.

Type 2 Descriptor Fields

NEXT Points to the next type 2 descriptor on a circular chain.

CHANNELS Points to the first subchannel descriptor 1007 with data outputallocated to the terminal which this type 2 descriptor relates.

RSTAT Contains a status indicator for the input process.

RTIME Contains the time, in units of 250 microseconds at which the lastinput was received.

RSELCH Points to the subchannel descriptor 1007 selected for data input.

RSEQ Contains the sequence number expected in the next data packetreceived.

SSTAT Contains a status indication for the data output process.

STIME Contains the time, in units of 250 microseconds at which the lasttransmission was made.

SSELCH Pointer to the sub-channel descriptor 1007 selected for dataoutput.

SELNO Contains the number of the channel currently selected for dataoutput.

SSEQ Contains the sequence number used in the last data transmission.

ID Contains, in its most significant 8 bits the ID to be used forpackets transmitted.

LOOP Points to the type 1 descriptor for the line with which this type 2descriptor is associated.

V.IN Contains minus one times the number of packets not yet received butwhose receipt has been authorized.

A.IN Contains the number of packets whose receipt can be authorizedafter receipt of the bundle currently being received.

V.OUT Contains minus one times the number of packets not yet transmittedbut whose transmission has been authorized.

A.OUT Contains the number of packets that can be sent after completionof the current bundle.

N.OUT Contains the maximum bundle size for data output.

N.IN Contains the maximum bundle size for data input.

TRCHAIN Pointer to the next trunk descriptor 1005 of the sametransmission line.

Subchannel Descriptor Fields

NEXT Points to the next subchannel descriptor 1007 of the same terminalinterface unit or of the same transmission line.

SINK Pointer to the type 2 descriptor to which data output is to bedirected.

DATAQH Pointer to the data output queue entry 1016 currently at the headof the queue.

DATAQT Pointer to the data output quenue entry 1016 following the lastactive queue entry.

NEXTOUT Pointer to the data output queue entry 1016 from which data isnext to be taken for output.

VOL This 16 bit value contains, in the last significant eight bits acount of the active entries in the data output queue. In the mostsignificant eight bits is a count of the packets which are the ends of amessages.

RATE This contains the minimum number of packet times that must elapsefor each packet of data transmitted.

COSTAT A status indicator for the subchannel. It indicates the statusfor data output processing.

CRSTAT A status indicator for data output processing of the subchannel.

M.IN The number of packet buffers assigned to the subchannel at thestart of burst transmission.

M.OUT The number of packets that should be collected before startingtransmission of data.

ALLOC The maximum number of packet buffers that can concurrently beassigned to the subchannel.

MAXN.IN The maximum bundle size for data input.

MAXN.OUT The maximum bundle size for data output.

CHANNO The number used to identify the channel to the receiving terminalor trunk.

SLOOP Pointer to the type 1 descriptor to which this subchannel relates.

Packet Buffer Fields

NEXT Pointer to the next packet buffer in one chain.

TERM Pointer to the type 2 descriptor to which the packet in this packetbuffer relates.

IDW A copy of the first two bytes of the data packet.

DLENGTH A copy of the third and fourth bytes from the data packet.

BODY An area of 17 words used to hold the data and checksum from a datapacket.

Miscellaneous Fields Used by the Control Computer

TIME This location is increased by one for each 250 microsecond intervalthat passes.

SCANTIME This contains minus one times the time that must elapse beforethe next activation of the timeout routine.

SCANNED Points to the type 2 descriptor last processed by the timeoutroutine.

FREESPACE All those packet buffers not actually in use are chained, bytheir NEXT fields, and the first is pointed to form FREESPACE.

UNASSIGNEDSPACE Contains a count of the number of packet buffers thathave not been assigned to any subchannel.

FREE32 A pointer to the first of a chain of 32 word storage areas thatare all currently not in use.

FREE4 A pointer to the first of a chain of unused four word storageareas.

COUNT4 A count of the number of four word areas in the chain FREE4.

LOOPLIST The address of a 256 location index containing pointers to type1 descriptors. Each such descriptor has an identity which is also theposition of the pointer to it contained in this index.

SWLIST The address of a 256 location index relating to the 256 possibleswitching unit identities. An entry in this list is a pointer to thesubchannel to be used to send messages to the switch in question.

SPACEDEBT This contains minus one times the maximum space allocationthat can be made to new virtual channels.

MESSAGE FORMATS USED FOR COMMUNICATION WITH THE CONTROL COMPUTER PROGRAM

The control computer program that uses the above described datastructures begins its operation with respect to a particularcommunication by responding to a request for the virtual allocation of atransmission path, and ends that operation by deallocating the path.This process requires communication between the control computer programand the remainder of the system. This communication uses messages havingstandard formats which are passed to the control computer 30 of theswitching unit 10. These messages are sent by both the digital device18, termed the "calling device," which is initiating the data transferand the digital device 18, termed the "called device" which is toreceive the data. Each messages comprises thirty-two bytes with thethirty-second byte being appropriately identified as an end-of-messageas was discussed hereinbefore in conjunction with FIG. 11C.

Four different messages are used. A "connect" message is sent by thecalling device to its associated switching unit to initiate channelallocation. An "accept" message is sent by the called device to itsassociated switching unit in response to the connect message if thecalled device is willing to accept data from the calling device.Otherwise, the called device sends a "reject" message. An "end-of-call"message is used by either the calling device or the called device todeallocate a channel.

When a calling device wishes to obtain allocation of a new channel itsends a connect message to the associated control computer. That messagecarries identification information which uniquely specifies the calleddevice. The control computer transmits the connect message, to thecalled device. A function code in the first byte of the message allowsthe called device to identify the message as a connection request. Ifthe called device wishes to accept the connection request, it addscertain information to the connection request, changes the function codeto indicate acceptance, and returns the updated message to the controlcomputer associated with the called device. If the called device wishesto reject the connection request, the function code in the request ischanged to indicate rejection and the message is returned to the controlcomputer.

An acceptance message contains all the information required by all ofthe switching units in the communication path to allocate one virtualchannel. When acceptance is obtained, the acceptance message is returnedin the calling device and at the same time the virtual channel isallocated. This is done on a link-by-link basis. Communication can startat any time after the calling device receives the acceptance message. Inthe case of a rejection, the rejection message passes from the calleddevice to the calling device without further action on the part of anyswitching unit in the communication path.

Either the called or the calling device may cause a virtual channel tobe deallocated by sending an end-of-call message to its associatedcontrol computer. That message is transmitted to the other device. Asthat transmission takes place, the virtual channel is deallocated on alink-by-link basis. Any data currently in transit on the virtual channelis lost.

As previously mentioned, by convention, all communication with thecontrol computer must be made on channel zero and all messagestransmitted from the control computer to a digital device are sent onthat devices' channel zero.

A message of thirty-two bytes comprises two sixteen-byte parts. Thefirst sixteen bytes contain a specification of the virtual channel forthe calling device; the second sixteen bytes contain a specification ofthe virtual channel for the called device. The first byte, termedFUNCTION, of the specification for the calling device contains afunction code indicating which type of message is being sent. IfFUNCTION is one it indicates a connect request, if two it indicates anacceptance, if three it indicates a rejection, and if four it indicatesan end-of-call. The remaining bytes of the two sixteen bytespecifications are used in the same manner. The values will, of course,depend on whether the device being specified is the calling or thecalled device. These remaining bytes are as follows.

The second byte of a specification, termed AOUT, contains the amount ofpacket buffer storage space that is to be used in each switching unitthrough which the virtual channel passes. This number specifies aparticular multiple of thirty-two bytes. The packet storage space isused to buffer all data passing away from the device in whosespecification the number appears.

The third byte, termed "MIN," specifies, as a multiple of thirty-two,the number of bytes of packet storage space to be assigned at the startof each burst transmission. It applies to bursts of transmission awayfrom the device in whose specification the number is contained.

The fourth byte, termed "NOUT," specifies, as a multiple of thirty-two,the number of bytes that should be collected in the switching unitbefore the start of delivery to the device in whose specification thisfourth byte appears. In the case that a complete message contains fewerbytes than are indicated in this specification, delivery of the messagewill start when all of it has been assembled in the switching unit.

The fifth byte, termed "RIN," specifies the maximum rate at which thedigital device to which the specification applies will accept datapackets on the particular channel being specified. That rate is given asa multiple of six miscroseconds and is the time allowed for the deliveryof one byte of data.

The sixth byte, termed "ROUT", specifies the expected maximum rate ofdata output during burst transmission. This rate also is expressed as amultiple of six microseconds and is the anticipated delivery time perbyte transmitted.

The seventh, eighth and ninth bytes, termed "SWITCHNO," "LINENO," and"TERMINALNO," respectively, uniguely identify the digital device towhich the specification relates. The SWITCHNO byte contains the identityof the switching unit to which the digital device is attached, theLINENO byte specifies the transmission loop on that switch, and theTERMINALNO byte contains the terminal interface unit ID.

The tenth byte, termed "CHANNELNO," specifies the channel number to beused by the digital device when communicating on the new virtualchannel.

The eleventh through sixteenth bytes of a message are reserved forswitching unit use. The eleventh and twelfth bytes together form asixteen-bit value, termed "LOOPD," which is a pointer to a type 1descriptor. The thirteenth and fourteenth bytes together form asixteen-bit value, termed "TERMINALD" which is a pointer to a type 2descriptor. The fifteenth and sixteenth bytes together form asixteen-bit value, terminal "TRUNKN," which uniquely identifies thechannel on a per-switching-unit basis.

The above-described data structures and message formats are used by thecontrol computer program in the manner shown in the flow charts of FIGS.18A-25N. These flow-charts describe the various routines and subroutinesthat make up the control computer program. The data output routine shownin FIGS. 21A and 21B is primarily responsible for implementing the datahandling portion of the α process as performed by the control computer,while the data input routine shown in FIGS. 20A and 20B is primarilyresponsible for implementing the data handling portion of the β process.The remaining routines and subroutines implement the remainder of thesetwo processes.

As previously mentioned, the Tempo 1 compouter utilized in theillustrative embodiment of this invention is multiprogramed. Theaforementioned routines and subroutines are thus actually divided intotwo subprograms, the level 1 subprogram and the level 2 subprogram.These subprograms are interrupt-driven with the level 1 subprogramhaving priority over the level 2 subprogram and serving to set theinterrupt that drives the level 2 subprogram.

The routines and subroutines of the control computer program are shownin FIGS. 18A-25N on a functional basis. Various of the routines containboth level 1 and level 2 instructions. The level 1 instructions dealwith the synchronous transmission lines 12 and transmission loops 14shown in FIG. 2A. In fact, there is a complete set of level 1instructions for each transmission line 12 and transmission loop 14connected to control computer 30. The appropriate set is executed inresponse to the interrupt that is generated by a signal from one of theline terminating units 31 shown in FIG. 2A. That is, each lineterminating unit 31 attached to control computer 30 controls its ownindividual interrupt line which activates the copy of the level 1instructions associated with that particular line terminating unit 31.Since time is of the essence in dealing with the synchronous loops 14and lines 12, the level 1 subprogram instructions are given higherpriority than the level 2 subprogram instructions.

The routines and subroutines of the control computer program may beimplemented in accordance with this illustrative embodiment by using theinstruction set of the Tempo 1 computer. As will be obvious to those oforidinary skill in the art, the flow charts of FIGS. 18A-25N could beprogrammed in many differently detailed ways to execute the indicatedprocesses. Indeed, the detailed steps in the flow charts could beaccomplished in a plurality of different ways. These will be obviousfrom the discussion below of FIGS. 18A-25N taken in conjunction with thedescriptions of the Tempo 1 computer that are provided in the Tempo 1Interface Reference Manual, TA-1000-969, and in the Tempo Programmer'sReference Manual, E0002. Although the many ways of accomplishing thedetailed steps that must be performed by control computer 30 will beobvious to those of ordinary skill, one particular sequence of suitableTempo program instructions that may be used is shown in the familiarhexadecimal form in the listing of Appendix B. It can be seen that thislisting contains two copies of the level 1 instructions and thus iscapable of handling a single transmission loop 14 and a singletransmission line 12. The listing of Appendix B was limited to two suchcopies of the level 1 instructions for brevity. The necessary additionalcoding for other loops 14 and lines 12 will be obvious to those ofordinary skill.

Turning then to the flow charts of FIGS. 18A-25N, it can be seen thatthese flow charts use the same symbols as were used in the flow chartsof FIGS. 12-16B. Additionally, the rectangular operation block symbol isalso used in FIGS. 18A-25N for the operation of calling a subroutine.Further, a hexagon is used to indicate a computed branch point whichuses a computed value to determine its branch point.

CALL MANAGEMENT ROUTINE OF THE CONTROL COMPUTER PROGRAM

FIGS. 181-18D are a flow chart of the call managemnt routine.

All bytes contain numeric values expressed in the binary notation. Aswill be obvious to those of ordinary skill in the art, other messageformats and other notations can be used without departing from thespirit and scope of this invention.

This routine handles all control messages, allocates virtual channels,and subsequently de-allocates them. The routine, which begins at block1030, is a level 2 routine. This routine, like the others in the controlcomputer program, uses the parameter "L." This parameter is a pointer tothe type 1 descriptor 1012 as shown in FIG. 171 which corresponds to theloop or line with which the current execution of the routine isassociated. In the case of the call management routine, it processes thedata output attention queue 1011 shown in FIG. 17H associated with thecontrol unit descriptor 1002. The pointer of that descriptor is storedin location L.

Block 1031 updates the field DXLAST of the control unit descriptor sothat it then contains the position of the next entry to be processed.Since the queue is in consecutive locations and the number of theselocations is DXLENGTH, the position of the next entry is obtained byadding one to DXLAST modulo DXLENGTH. This function is indicated inblock 1031 in FIG. 18A by the term "|DXLAST(L)+1|_(DXLENGTH)." It is tobe noted that DXLAST(L) means "the DXLAST field of the descriptorpointed to by the pointer stored in location L.

Block 1032 then copies the next queue entry into temporary storagelocation Q. If this entry contains zero, then no action has beenrequested. Conditional branch point 1033 tests for this condition andtransfers control to the end of the routine at terminal indicator 1056shown in FIG. 18B if no action is required. If the attention request hasbeen properly made the status field COSTAT in the subchannel descriptorwhose pointer is in Q will be equal to 1. Conditional branch point 1034transfers control to the end of the routine at terminal indicator 1056shown in FIG. 18B if the status value is not 1. Conditional branch point1035 then checks to see that there is in fact a data packet waiting tobe processed. The field NEXTOUT in the subchannel descriptor pointed toby Q points to the next data output queue entry 1016 shown in FIG. 17Lto be processed. The queue of data waiting to be output will be empty ifthat entry is the same as the one pointed to by DATAQT of the subchanneldescriptor. When there is no data to process, conditional branch point1035 transfers control to the end of the routine at terminal indicator1056 shown in FIG. 18B. Otherwise block 1036 sets temporary location Requal to the pointer of the queue entry to be processed.

The field DBLK of the data output queue entry points to the packetbuffer to be processed. The pointer to that buffer is put in temporarylocation P by block 1037. The data in that packet buffer is a controlmessage. In block 1038 temporary location M_(A) is set equal to thepointer to the first specification in that message, and temporarylocation M_(B) is set equal to the pointer to the second specificationin the message. Block 1038 then transfers control to computed branchpoint 1039.

The point to which computed branch point 1039 switches control dependsupon the value of the FUNCTION code contained in the first byte of themessage. If the FUNCTION code is 0, control passes to block 1040, ifFUNCTION code is 1 control passes to conditional branch point 1057,shown in FIG. 18C, if the FUNCTION code is 2 control passes to block1068, shown in FIG. 18D, and if the FUNCTION code is 3 control passes toblock 1069, also shown in FIG. 18D.

Consider first the sequence starting at block 1040. This is obeyed whena connect message is received. Block 1040 calls subroutine DECODE.ROUTE,with M14 set equal to the pointer in M_(b), which is used to set up theloop descriptor pointer LOOPD, the terminal descriptor pointer,TERMINALD, and the trunk identification number TRUNKN in thespecification pointed to by M_(B). This subroutine returns the pointerto the subchannel description to be used for control messages destinedfor the called device of the received connect message. This is stored inthe temporary location X and control then passes to block 1041 shown inFIG. 18B.

Block 1041 computes the checksum for the data packet pointed to by P andstores it in the word following the sixteen words of data in the packet.The data output attention queue entry is then set to 0 by block 1042 andthe status field COSTAT in the subchannel descriptor pointed to by Q isset to 0 by block 1043 indicating that there is now no attention requestoutstanding for the subchannel. Control is then transferred to block1044.

The operation performed by block 1044 is seen in flow chart 18B to bedefined as NEXTOUT(Q)=NEXT(NEXTOUT(Q)). The meaning of this notation isas follows:

First consider the expression NEXTOUT(Q). NEXTOUT(Q) denotes the fieldNEXTOUT in the subchannel pointed to by the pointer in location Q.NEXTOUT(NEXTOUT(Q)) thus denotes the field NEXT which is pointed to bythe pointer in location NEXTOUT.

Considering now the entire expression shown in block 1044, it will beremembered that the expression "A═B" is understood by those of ordinaryskill in he programming art to mean "store the contents of location B inlocation A." Thus a symbol to the left of the "═" symbol denotes alocation while a symbol to the right denotes the contents of a location.

Thus block 1044 is seen to transfer the contents of NEXT to locationNEXTOUT. Control lis then transferred to conditional branch point 1045.

Conditional branch point 1045 transfers control to conditional branchpoint 1047 if the data output queue of the subchannel pointed to by Q isempty. That condition exists if the fields NEXTOUT and DATAQT are equal.If they are not equal control passes to block 1046 where a call is madeon the subroutine REQOUT, with C7 set equal to the pointer in Q, toreplace subchannel Q in the data output attention queue.

After block 1046, conditional branch point 1047 tests whether adestinatin for the control message was obtained. If location X contains0 control passes to block 1062 shown in FIG. 18C. Otherwise, block 1048copies the contents of field DATAQT in subchannel descriptor pointer toby X into temporary location B. Location B now contains the pointer ofthe next usable entry in the data output queue for subchannel X. TheTYPE field in that entry is set equal to 2 by block 1049, and block 1050sets the DBLK field to point to the packet buffer pointed to by P.Having thus constructed a new queue entry, the field VOL of thesubchannel description pointed to by X is increased in value by thehexadecimal value $101 by block 1051, and the field DATAQT of thesubchannel X is set to point to the next queue entry. The pointer ofthat entry is to be found in the field NEXT(B). Conditional branch point1053 is then obeyed to check whether the subchannel field COSTAT isequal to 2. If so, control passes to block 1054, otherwise it passes toblock 1055. Block 1054 calls subroutine S.BURST.OUT, with C(3)═X, whichperforms the housekeeping associated with the start of a new burst ofdata on subchannel X.

Block 1055 calls subroutine REQOUT to place subchannel X in theappropriate data output attention queue.

After either block 1054 or block 1055 has been obeyed, control passes tothe end of the call management routine at terminal indicator 1056.

It was mentioned above that, upon recognizing a FUNCTION code of 1,computed branch point 1039 transfers control to conditional branch point1057 shown in FIG. 18C. The sequence starting at that point handles theallocation of a virtual channel as it transmits the acceptance messageback to the calling device. Conditional branch point 1057 tests whetherthere is sufficient storage space available for the data output queueentries that will be needed by the virtual channel. The number ofentries required equals the sum of the message fields AOUT for each ofthe two devices. Since the queue entries are four word items, the sum iscompared with COUNT4, the number of free four word units on the freestore chain FREE4. If insufficient space is available, conditionalbranch point 1057 transfers control to block 1062. Conditional branchpoint 1058 next checks that there is a thirty-two word block of storeavailable to hold the channel descriptor for the new virtual channel. Ifno such block exists, control passes to block 1062. Otherwise block 1059is obeyed.

Block 1059 calls the DECODE.ROUTE subroutine which is given a pointer tothe specification for the calling device to the requested channel. Thesubroutine sets up loop descriptor pointers, the terminal descriptorpointer, and the trunk number in the specification pointed to by M_(A).It returns as its result the subchannel pointer of the subchannel to beused to send control messages to that device. This result is stored intemporary storage location X.

Block 1060 calls upon the subroutine TRACE.ROUTE which determines theloop descriptor pointer and terminal pointer of the calling device tothe connection and places these data in the specification pointed to byM_(B). The subroutine returns a result that in the pointer of anothersubchannel descriptor if one already exists for the same channel numberas is used by the called device. Next conditional branch point 1061transfers control to block 1062 if such a subchannel already exists.Block 1064 next obtains one block of 32 words from the free store listFREE32. To do this it copies the pointer currently in FREE32 intotemporary storage location C and copies the pointer in the field NEXT ofthe block pointed to by C into location FREE32. Block 1065 uses thesubroutine CREATE.SUBCHANNEL to construct the subchannel descriptor forthe subchannel which transfers data from the called device to thecalling device. The subchannel descriptor is constructed in the sixteenwords starting at that word pointed to by temporary location C. Block1066 then uses the subroutine CREATE.SUBCHANNEL to construct thesubchannel descriptor for the subchannel that transfers data from thecalling device to the called device. That descriptor is made up of thesixteen locations which are the last sixteen in the thirty-two locationspointed to by C.

Having thus constructed the channel descriptors, the call managementroutine transfers the trunk number from the field TRUNKN from thecalling device's specification to the same field of the called device'sspecification, as shown in block 1067. The sequence then ends with atransfer of control to block 1041 shown in FIG. 18B which is the firstof the sequence which sends the control message out on the subchannelpointed to by X.

Consider now the sequence that starts with block 1062. That sequence isobeyed whenever the control message has to be abandoned. First in thesequence, a call is made on the subroutine RELEASE.SPACE as shown inblock 1062. That subroutine is given the pointer P of the packet buffercontaining the message to be discarded. The routine returns the packetbuffer to the free storage list FREESPACE. Block 1063 next updates thedata output queue pointers NEXTOUT in the subchannel Q that held themessage. To do this, it copies the pointer in the field NEXT of thequeue entry pointed to by NEXTOUT into the field NEXTOUT. Control thenis transferred to the end of the call management routine at terminalindicator 1056.

It was seen from the above that control is transferred to block 1068shown in FIG. 18D if a reject message is received. The reject message ispassed directly back to the calling device without any further action onthe part of the call management routine. To effect this, block 1068 usessubroutine DECODE.ROUTE to obtain the pointer, in X, of the subchannelon which control messages to the calling device should be sent. Thatpointer is the computed result of the subroutine DECODE.ROUTE. Afterdoing this, the call management routine transfers control to thesequence beginning at block 1041.

Control messages with a FUNCTION code of 3 are used to terminate aconnection and to deallocate a virtual channel. Upon detecting one ofthese messages computed branch point 1039 transfers control to block1069. Block 1069 shown in FIG. 18D calls subroutine TRACE.ROUTE tocompute the loop descriptor pointer and terminal descriptor pointer forthe calling device. This data is stored in the specification for thecalling device as pointed to by M_(A). The result of the subroutineTRACE.ROUTE is the pointer of the subchannel to be deleted. If no suchsubchannel is found, conditional branch point 1070 transfers control toblock 1062. Otherwise, control passes to block 1071. The pointers of thetwo subchannels in the pair making one full-duplex channel differ bysixteen and, given the pointer of one, the other can be found by anEXCLUSIVE OR operation. In block 1071 the pointer of the subchannelwhich sends data to the called device is stored in temporary location C.Conditional branch points 1072 and 1073 transfer control to the end ofthe call management routine at terminal indicator 1056 if either of thestatus fields COSTAT in the two subchannels is equal to 1. Block 1074transfers the value in field CHANNO of the subchannel pointed to by C tothe TRUNKN field in the specification pointed to by M_(B). If TRLIST inthe type 1 descriptor pointed to by SLOOP in the subchannel descriptorpointed to by C is negative, then the type 1 descriptor is a loopdescriptor and conditional branch point 1075 transfers control to block1077. Otherwise it is a line descriptor and control passes to block1076. Block 1076 sets in X the pointer to the subchannel descriptorwhich is pointed to by field SIGCH of the above-mentioned linedescriptor. Control then passes to block 1081 which calls subroutineREMOVE.SUBCHANNEL to deallocate the subchannel pointed to by C. Block1082 then uses the same subroutine to deallocate the other subchannel ofthe same channel. In blocks 1083 and 1084 the thirty-two word blockcontaining the two subchannel descriptors is added to the free storechain FREE32. The pointer of the block is obtained by removing the leastsignificant five bits of the pointer in C. The current head of the freestore chain is copied from FREE32 to NEXT of the block and the pointerof the block is set in FREE32. Control then passes to block 1041.

When the subchannel descriptor pointed to by C is associated with a loopdescriptor, conditional branch point 1075 passes control to block 1077.In that block temporary location X is set equal to the pointer of thefirst channel in the chain from the field CHANNELS of the terminaldescriptor whose pointer is in SINK of subchannel descriptor pointed toby C. The loop consisting of conditional branch points 1078 and 1079 andblock 1080 then searches for the subchannel descriptor with CHANNO equalto 0. In each cycle around the loop, block 1080 sets equal to thepointer in NEXT of the subchannel previously inspected. Conditionalbranch point 1078 transfers control out of the loop if the end of thechain of subchannels is reached. Conditional branch point 1079 transferscontrol out of the loop if a subchannel descriptor with CHANNO equal to0 is found. The pointer of the descriptor so found is left in X. Whencontrol is transferred out of the loop it goes to block l081 previouslydescribed.

SUBROUTINE DECODE.ROUTE OF THE CONTROL COMPUTER PROGRAM

The subroutine DECODE.ROUTE is shown in FIG. 19A. This subroutine isused to examine the specification for one device to a channel allocationrequest, that device's specification being pointed to by M14. Thesubroutine also computes a result which is the pointer to the subchanneldescriptor which should be used to send control messages to the devicespecified.

The subroutine begins at terminal indicator 1090. Conditional branchpoint 1091 tests whether the field SWITCHNO specified for the device isequal to the unique identifying number for the switching unit in whichthe subroutine is being executed. If so, control passes to block 1097.If the call is being made to a device attached to another switchingunit, block 1092 is used to obtain from the index of switching units thechannel number of the channel to be used for messages to that switchingunit. That index is SWLIST. Block 1092 sets C14 equal to the contents ofthe entry in SWLIST whose position in that list is equal to theswitching unit number specified in the device specification. If C14 isset equal to 0, conditional branch point 1093 transfers control to block1095. Block 1094 sets the loop descriptor pointer in the specificationpointed to by M14 equal to the pointer in SLOOP of the subchanneldescriptor pointed to by C14. The value in C14 is returned as the resultof the subroutine as indicated in block 1095, and control is transferredto the end of the subroutine at terminal indicator 1096.

When the switching unit specified in the specification M14 is that ofthe switching unit in which this subroutine is being obeyed, controlpasses to block 1097. The line number specified in the specification M14is then inspected and used to determine the position of an entry in theindex LOOPLIST. In block 1097 the content of that entry is transferredlocation L14. L14 now contains either the pointer of the specified loopdescriptor, or 0 if no such loop exists. Conditional branch point 1098transfers control to block 1634 if the index entry is 0. The loopdescriptor pointer for the specification pointed to by M14 is set equalto the value in L14. Next, the terminal number contained in thespecification pointed to by M14 is transferred to location N14. Thatvalue is then used in block 1631 as the position of an index entry inthe terminal index pointed to by TERMINALS of the loop descriptorpointed to by L14. In block 1631 the contents of that entry is copied tolocation T14. If T14 is 0, control is transferred to block 1634 byconditional branch point 1632.

Block 1634 then sets C14 equal to 0 and transfers control to block1639A. If T14 is non-zero block 1633 is obeyed. That block sets thefield TERMINALD in the specification pointed by M14 equal to T14. Next,C14 is set equal to the first subchannel pointer in the list CHANNELSfor the terminal descriptor pointed to by T14. The loop consisting ofconditional branch points 1636 and 1637, and block 1638 serves to searchout the subchannel with CHANNO equal to 0. Each time round the loopblock 1638 sets the pointer of the next subchannel to be inspected inC14. That pointer is obtained from the field NEXT of the precedingsubchannel currently pointed to by C14.

Conditional branch point 1636 transfers control out of the loop if C14is 0. Conditional branch point 1637 transfers control out of the loop ifthe subchannel with a 0 in the CHANNO field is found. After this searchhas terminated, block 1639A is obeyed. From that block it is seen thatthe result of the subroutine is the value in C14. Terminal indicator1639 is the end of the DECODE.ROUTE subroutine.

TRACE.ROUT SUBROUTINE OF THE CONTROL COMPUTER PROGRAM

The subroutine shown in FIG. 19B is the TRACE.ROUT subroutine. Itcomputes the loop descriptor and terminal descriptor pointers for thedevice that is the source of the control message now being processed andplaces these in the specification point to by M15. The subroutinereturns a subchannel pointer as its result, that pointer being of thesubchannel specified by the specification M15.

The subroutine starts at block 1640. In block 1641 it is seen that thetype 1 descriptor pointer SLOOP in the subchannel descriptor pointed toby Q is copied into LOOPD for the specification M15. Conditional branchpoint 1642 tests whether the type 1 descriptor is a loop or line. If itis a loop the field TRLIST in the descriptor is negative and controlpasses to block 1645. If the type 1 descriptor is a line, control passesto block 1643. In block 1643 temporary storage location N15 is set equalto the trunk number in the specification pointed to by M15. Then inblock 1644 temporary storage location C15 is set equal to the pointerCHLIST in the loop descriptor pointed to by SLOOP in subchanneldescriptor Q. Control then passes to conditional branch point 1648. Thatbranch point together with block 1650 form a loop in which a search ismade for the subchannel descriptor with CHANNO equal to the value inN15. Each time round the loop block 1650 sets C15 equal to the pointerof the next subchannel and that pointer from the field NEXT of thesubchannel currently pointed to by C15. Conditional branch point 1648transfers control to block 1649A if the field CHANNO in the subchanneldescriptor pointed to by C15 is equal to the value in N15. In block1649A it is shown that the result of the subroutine is the value in C15.After block 1649A, control passes to the end of the subroutine atterminal indicator 1649.

REMOVE.SUBCHANNEL SUBROUTINE OF THE CONTROL COMPUTER PROGRAM

Subroutine REMOVE.SUBCHANNEL is shown in FIG. 19C. This subroutine isused to deallocate a single subchannel. The subroutine requires a singleinput parameter C17 which is a pointer to the descriptor for thesubchannel to be deallocated. The subroutine begins at terminalindicator 1125. Conditional branch point 1126 transfers control to block1134 if subchannel C17 is allocated to transmit data to a TIU. That factcan be determined by inspecting the field TRLIST of the type 1descriptor pointed to from the field SLOOP in the channel descriptor. IfTRLIST is negative the type 1 descriptor is a loop descriptor, otherwiseit is a line descriptor. If the type 1 descriptor is a line descriptorcontrol is transferred to block 1127 where a pointer to that type 1descriptor is copied into the temporary storage location L17. In block1128 the temporary storage location A17 is set equal to the pointercontained in the field CHLIST of the type 1 descriptor pointed to byL17. Conditional branch point 1129 then transfers control to conditionalbranch point 1132 if the pointers in locations A17 and C17 are notequal. If they are equal then the subchannel pointed to by C17 isremoved from the chain starting at field CHLIST by copying the pointerfrom NEXT in the subchannel C17 to the field CHLIST in the linedescriptor pointed to by L17. Control then passes to block 1138.

The sequence that begins with block 1134 removes the subchannel from thechain of subchannels for the TIU descriptor with which it is associated.Block 1134 sets in T17 a pointer to the TIU descriptor which is pointedto from field SINK of the subchannel descriptor pointed to by C17. Block1135 copies into A17 the pointer from field CHANNELS of the TIUdescriptor addressed by T17. Conditional branch point 1136 transferscontrol to block 1137 if the pointer now in C17 equals that in A17. Ifthey are unequal control passes to conditional branch point 1132. Block1137 copies the pointer from NEXT of the subchannel descriptor addressedby C17 into CHANNELS of the TIU descriptor pointed to by T17. Controlthen passes to block 1138.

The loop comprising block 1131 and conditional branch point 1132searches for the chain position occupied by subchannel descriptor C17.In each cycle of the loop, block 1131 sets a pointer to the subchanneldescriptor previously inspected in A17 taking that pointer from the NEXTfield of the subchannel descriptor previously pointed to by A17.Conditional branch point 1132 transfers control out of the loop to block1133 when NEXT of the subchannel descriptor A17 is that addressed byC17. Block 1133 copies the pointer from NEXT in subchannel descriptorC17 into NEXT of subchannel descriptor A17. Control then passes to block1138.

The number of queue entries in the data output queue for subchannel C17is to be found in the field ALLOC. That number is added, by block 1138,to the storage location COUNT4. In block 1139 a pointer from fieldNEXTOUT of he subchannel descriptor pointed to by C17 is copied intoB17. Block 1140 places on the free store chain starting at locationFREE4 all queue entries attached to the subchannel descriptor pointed toby C17. To do this, it sets NEXT in the queue entry pointed to by PREVin the queue entry pointed to by B17, then copies the pointer from B17to FREE4. Control then passes to the end of the subroutine at terminalindicator 1141.

CREATE.SUBCHANNELL SUBROUTINE OF THE CONTROL COMPUTER PROGRAM

Subroutine CREATE.SUBCHANNEL, shown in FIG. 19D, is used to allocate onevirtual subchannel by completing the subchannel descriptor pointed to byC16. The specification for the destination of data on that subchannel ispointed to by M16. The subroutine starts at terminal indicator 1145.Conditional branch point 1146 transfers control to block 1148 if thepointer in M16 equals that in M_(A), otherwise it transfers control toblock 1147. In block 1148 N16 is set equal to the pointer in M_(B), andin block 1147 N16 is set equal to the pointer in M_(A). Block 1149 setsthe ALLOC field of the subchannel pointed to by C16 equal to thespecification field AOUT in the specification pointed to by N16. Block1150 sets the M.IN field of the subchannel pointed to by C16 equal tothe value in the MOUT field of the specification pointed to by N16.Conditional branch point 1151 transfers control to block 1155 if thefield ROUT of the specification pointed to by N16 is greater than apre-specified constant RLIMIT, and block 1155 sets field MAXN.IN of thesubchannel pointed to by C16 equal to 1. Conditional branch point 1152transfers control to block 1153 if the field MOUT of the specificationpointed to by N16 contains a value greater than thirty-two, and block1153 sets thirty-two in the field MAXN.IN of the subchannel pointed toby C16. Block 1154 copies the value from the field MOUT of thespecification pointed to by N16 into MAXN.IN of the subchannel pointedto by C16.

Block 1156 makes a call on subroutine FIND.QUEUE to obtain in Q16 apointer to the chain of queue entries. The length of that chain is setin L18 and is one more than the value in the AOUT field of thespecification pointed to by N16. Block 1157 then copies the value fromQ16 into the fields NEXTOUT, DATAQH and DATAQT, respectively, of thesubchannel pointed to by C17. In block 1158 0 is set in field VOL of thesubchannel pointed to by C16. Then the values 2 and 1 are set in thefields COSTAT and CRSTAT respectively of the subchannel descriptorpointed to by C16. Block 1161 copies the pointer from LOOPD of thespecification pointed to by M16 into the field SLOOP of the subchannelpointed to by C16. If the field TRLIST of that type 1 descriptor isnegative, conditional branch point 1162 transfers control to block 1175.Otherwise, conditional branch point 1163 checks to see if the field RINof specification M16 is greater than the prespecified constant RLIMIT.If it is greater, control is transferred to block 1168, otherwise block1164 is obeyed. Block 1164 copies from the field RIN of thespecification pointed to by M16 into the field RATE of subchannel C16.Conditional branch point 1165 then tests the field MIN of thespecification pointed to by M16 and if that field is greater thanthirty-two, control passes to block 1166. Block 1167 copies from fieldMIN of the specification pointed to M16 into MAXN.OUT of the subchannelpointed to by C16. Block 1166 copies thirty-two into MAXN.OUT of thesubchannel pointed to by C16. After either of these two blocks, controlpasses to block 1170. It was seen that control could be transferred toblock 1168 from conditional branch point 1163. In block 1168 the fieldRATE of the subchannel pointed to by C16 is set equal to theprespecified constant RLIMIT. In block 1169 the value 1 is copied intofield MAXN.OUT of the subchannel pointed to by C16, then control istransferred to block 1170 shown in FIG. 19E.

In blocks 1170, 1171 and 1172 the three fields M.OUT, SINK and CHANNO ofthe subchannel pointed to by C16 are set equal to the values in fieldsMIN, TERMINALD and CHANNELNO, respectively, of the specification pointedto by M16. The field NEXT in the subchannel pointed to by C16 is thenset by block 1173 to be equal to the pointer in CHANNELS of the type 2descriptor pointed to from field SINK of the subchannel pointed to byC16. The field CHANNELS of the type 2 descriptor is then set equal tothe pointer in C16. Control then passes to the end of the subroutine atterminal indicator 1174.

Block 1175 is obeyed, as was indicated above, when conditional branchpoint 1162 determines that the field SLOOP of the subchannel pointed toby C16 points to a line descriptor. Blocks 1175, 1176 and 1177respectively copy values 1, and 0 into the fields M.OUT, RATE and SINKof the subchannel pointed to by C16. Conditional branch point 1178transfers control to block 1182 if the pointer in M16 is the same asthat in M_(A). Otherwise control passes to block 1179. Block 1179 copiesfrom the field TRUNKN in the specification pointed to by M16 into thechannel number field CHANNO of the subchannel pointed to by C16. Block1180 sets temporary location L16 equal to the pointer in SLOOP of thesubchannel pointed to by C16, Block 1181 copies the pointer from CHLISTin the line descriptor pointed to by L16 into the field NEXT of thesubchannel pointed to by C16 before copying the pointer from C16 intothe field CHLIST. After block 1181, control is transferred to the end ofthe subroutine at terminal indicator 1174.

When the pointers in M_(A) and M16 are equal, the sequence beginning atblock 1182 is obeyed. In block 1182 L16 is set equal to the pointer fromfield SLOOP of the subchannel pointed to by C16. A 1 is then added tothe field TRUNKDEBT for the line descriptor pointed to by L16. In block1184 temporary storage locations A16 and B16 are set equal to the valuein fields CHHIGH and CHLOW of the line descriptor L16. Block 1185 thensets temporary storage locations K16 equal to the value in field CHLISTof the line descriptor pointed to by L16. A pointer to the field CHLISTof the line descriptor is set in J16. The loop comprising conditionalbranch point 1186 through 1189 and blocks 1193 through 1195 searches foran unused channel identification number in the chain of subchanneldescriptors starting with that pointed to by K16. Conditional branchpoint 1186 transfers control to block 1190 if K16 contains 0.Conditional branch points 1187 then transfer control to block 1194 ifthe channel number in CHANNO of the subchannel descriptor addressed byK16 is either less than the value in B16 or not less than the value inA16. If the field CHANNO contains a value equal to that in A16,conditional branch point 1189 transfers control to block 1193.Otherwise, it transfers control out of the loop to block 1190. In block1193 the content of location A16 is increased by one. Next, block 1194copies the pointer from K16 to location J16. In block 1195 the pointerfrom field NEXT of the subchannel descriptor pointed to by K16 is copiedinto K16. Control then passes to block 1186.

As indicated above, the search for a spare channel identification numberends with a control transfer to block 1190. In block 1190 the fieldCHANNO of the channel descriptor pointed to by C16 is set equal to thevalue in A16. That value is then copied into the field TRUNKN of thespecification pointed to by M16. The subchannel pointed to by C16 isthen added to the chain of subchannels. This is done in block 1192 bycopying the pointer from C16 into the field NEXT of the subchanneldescriptor pointed to by J16, and by copying the pointer left in K16into the field NEXT of the subchannel pointed to by C16. Control then istransferred to the end of the subroutine at terminal indicator 1174.

FIND.QUEUE SUBROUTINE OF THE CONTROL COMPUTER PROGRAM

The subroutine FIND.QUEUE shown in FIG. 19F is used to obtain a newqueue comprising four word queue entries assembled into a circular chainby the fields NEXT and PREV, as was described hereinbefore. Thesubroutine takes one parameter from L18 and that is the length of thequeue required. The subroutine begins at terminal indicator 1660 shownin FIG. 19F. Block 1661 sets a pointer to the first free four word blockin T18, and block 1662 sets B18 equal to the same value. The loopcomprising blocks 1663 through 1666 takes the required number of fourword blocks from the chain starting at T18. Block 1663 copies thepointer from B18 to location E18. Block 1664 copies into B18 the pointerNEXT from the block currently pointed to by B18. Block 1665 then reducesthe content of L18 by 1. Conditional branch point 1666 then transferscontrol back to block 1663 if the value in L18 is still greater than 0.The pointer now in B18 is placed in the location FREE4. Block 1668 makesthe chain circular by setting the pointer in T18 into the field NEXT ofthe queue entry pointed to by E18. Block 1669 copies the queue entrypointer from T18 to B18. The loop comprising blocks 1760 to 1673 buildup the chain of reverse pointers in fields PREV of the queue. Block 1670sets the pointer from E18 into the field PREV of the queue entry pointedto by B18. Block 1671 copies the pointer from B18 to E18. Block 1672copies into B18 the pointer in the field NEXT of the queue entrycurrently pointed to by B18. Conditional branch point 1673 returnscontrol to block 1670 if the pointer in B18 does not equal that in T18.The pointer in T18 is returned as the result of the subroutine as shownin block 1674, and then control passes to the end of the subroutine atterminal indicator 1675.

DATA INPUT ROUTINE OF THE CONTROL COMPUTER PROGRAM

The data input routine is shown in detail in FIGS. 20A-20D. Referring toFIGS. 20A and 20C, it is seen that there are two program sequences inthis routine. The first one, starting with block 1200, is obeyed atlevel 1. The other one, starting at block 1240, is obeyed at level 2.

Considering first the program sequence obeyed at level 1, shown in FIG.20A, it is seen that this sequence is obeyed when the line terminatingunit 31 has a data packet ready for collection by control computer 30.First in that program sequence is conditional branch point 1201 where atest is made on the working store location RDBLOCK. If that location isnon-zero, then it will contain the address of a packet buffer which canbe used to store a new incoming data packet. If RDBLOCK is zero, thenthe data input routine must obtain a packet buffer from the communalsupply. Conditional branch point 1201 therefore transfers control toblock 1208 if RDBLOCK already contains the address of a packet buffer.Otherwise, control passes to block 1202.

In order to avoid timing problems, the sequence beginning at block 1201is obeyed with interrupts inhibited. The communical storage supplycomprises a chain of packet buffers with the address of the first packetbuffer stored in working store location FREESPACE.

In block 1203 it is seen that that address is copied into RDBLOCK, thenconditional branch point 1204 checks whether the address so obtained wasnon-zero. If it was, the address of the next packet buffer on the chainof free storage locations is copied by block 1205 into the storagelocation FREESPACE and in block 1206 interrupts are allowed. If the freestorage supply is empty, then conditional branch point 1204 transferscontrol to block 1207 where interrupts are allowed.

After block 1207, control passes to block 1214. Returning now to theusual course of events, after block 1206 is executed, control passes toblock 1208 where the first sixteen-bit work is read from lineterminating unit 31 into control computer 30 and stored in field IDW ofthe packet buffer addressed by RDBLOCK. Next, in block 1209, anothersixteen-bit word is read from the line terminating unit 31 into controlcomputer 30 and stored in field DLENGTH of the packet buffer addressedby RDBLOCK. The two sixteen-bit words read by blocks 1208 and 1209comprise the first four bytes of the incoming data packet. The last ofthese bytes is a checksum which is the EXCLUSIVE OR of the first threebytes. Therefore, if no errors have occurred during data transmission,the EXCLUSIVE OR of all four bytes as computed by block 1210 shouldyield a result of 0. A test of that case is made by conditional branchpoint 1211 where control is transferred around block 1212 to block 1213if the result is non-zeroand therefore indicates an error. When no erroris detected control passes from conditional branch point 1211 to block1212 where working store location RSTATE is set equal to 1 to indicatethat the input of the data is in progress.

The interconnection of the line terminating unit 31 and the Tempo Icomputer makes use of the high rate I/O feature described in theaforementioned Tempo programmers reference manual. Using the mechanismdescribed therein, the seventeen remaining words comprising thethirty-four remaining bytes of the incoming data packet are transferredautonomously into field BODY of the packet buffer pointed to by RDBLOCKas indicated in block 1213. When the autonomous transfer is complete,execution of the data input routine continues at terminal indicator 1214shown in FIG. 20B.

Conditional branch point 1215 tests the value of RSTATE which is equalto 1 if, in fact, a data packet was being read. If that was not thecase, conditional branch point 1215 transfers control to the end of thedata input routine at terminal indicator 1228. Otherwise, control passesto block 1216. The first byte of the data packet is contained in themost significant eight bits of the field IDW in the packet bufferpointed to by RDBLOCK. That byte, as shown in block 1216 is extractedand transferred to temporary storage location ID. The value so obtainedis the identity of a TIU, or trunk, and should not be greater than onehundred twenty-seven. If the contents of storage location ID exceed onehundred twenty-seven, then conditional branch point 1217 transferscontrol to the end of the data input routine at terminal indicator 1228.Otherwise control passes to block 1218.

Associated with the transmission line or loop on which the data packetarrived is a type 1 descriptor having the structure described above. Theaddress of that descriptor is contained in storage location L. In thatdescriptor the field TERMINALS contains the address of a list of thetype 2 descriptors relating to the terminals, or trunks, connected tothat transmission line. The address of the type 2 descriptor containedin the list entry whose position in the list is equal to the valuestored in temporary location ID relates to the TIU or trunk from whichthe data packet came. That descriptor address is transferred in block1218 to temporary storage location T.

As was seen above, the line terminating unit 31 computes a sixteen-bitchecksum of the data contained in the data packet and compares it withthe final sixteen bits in the data packet. Status line 245 shown in FIG.5E is used to test whether the comparison indicates that the datatransmission error occurred. Another test for the data transmissionerror can be made by examining the status derived from line 224 shown inFIG. 5D. That line will be non-zero if the byte assembler 64 shown inFIG. 5E detected in a bipolar format error during the receipt of thedata packet. Conditional branch points 1219 and 1220 test these errorconditions and transfer control to the end of the data input routine atterminal indicator 1228 if either type of error was detected. Otherwisecontrol passes to block 1221 where the field TERM in the packet bufferlocation addressed by RDBLOCK is set equal to the terminal descriptoraddress contained in temporary location T.

Having thus successfully read the data packet from the transmissionline, the level 1 sequence of the data input routine adds the packet toa queue associated with the type 1 descriptor relating to the line orloop on which the packet arrives. In order to avoid timing troubles,this action is taken with interrupt inhibited as indicated by locks 1222and 1224. The first-in-first-out queue is updated as shown in block1223. The last entry currently existing on that queue is addressed byfield DRTAIL in the type 1 descriptor addressed by L. To update thequeue, the field NEXT in the packet buffer pointed to by RDBLOCK is setequal to the address of the end of the queue. Then field NEXT in thepacket buffer currently at the end of the queue is set equal to theaddress contained in RDBLOCK. Finally, field DRTAIL in the type 1descriptor addressed by location L is set equal to the address of thenew end of the queue, namely, the address in RDBLOCK. Having thusdisposed of the incoming data packet, and having used the packet bufferpointed to by RDBLOCK, the data input routine now writes 0 in RDBLOCK asillustrated in block 1225 and clears working store location RSTATE asillustrated in block 1226. Finally, in block 1227, the level 1 sequenceof the data input routine sets an interrupt that will call the level 2subprogram to be obeyed. A simple device controller connected to theTempo I peripheral bus may be constructed in the manner which will beobvious to those of ordinary skill in the art so that when issued aTempo I EDF instruction it sets the appropriate interrupt line.

That part of the data input routine which is obeyed at level 2 is shownin FIG. 20C, starting at terminal indicator 1240. That sequence teststhe queue of data input packets stored in association with the type 1descriptor with address L and for each packet contained on that queueperforms the process starting at block 1240. Conditional branch point1241 checks whether the queue is empty by inspecting the field DRHEADcontained in the type 1 descriptor with the address contained in storagelocation L. If the queue is empty, the address contained in DRHEAD isequal to the address of the field DRTAIL in the same type 1 descriptor.If that is the case, control passes to the end of the data input routineat terminal indicator 1242. Otherwise control passes to block 1243.

The next action taken at level 2 is to remove one data packet from thequeue, pointed to by DRHEAD. That removal must be obeyed with interruptsinhibited if timing errors are to be avoided. Interrupts are thereforeinhibited at block 1243 and the data packet is removed from the queue inblock 1244. Finally, interrupts are allowed in block 1245. The specificaction taken in block 1244 is first to store in temporary location D theaddress of the packet buffer containing the data packet being removedfrom the queue. The address of that packet buffer is obtained from fieldDRHEAD in the type 1 descriptor whose address is in L. A new value isthen inserted in field DRHEAD of the type 1 descriptor, that addressbeing the contents of the field NEXT in the packet buffer now addressedby temporary location B.

Field TERM of the packet buffer addressed by B contains the address of atype 2 descriptor and in block 1246 this address is transferred totemporary location T. Next, in block 1247 the current time measured inunits of 250 microseconds is transferred in storage location TIME intofield RTIME in the type 2 descriptor whose address is now contained intemporary location T. The sequence number of the data packet can befound in the most significant six bits of the least significant byte infield IDW of the packet buffer addressed by B. That sequence number isextracted in block 1248 and stored in temporary location S.

Next, conditional branch point 1249 compares S with field RSEQ in thetype 2 descriptor whose address is contained in T. If these two six-bitnumbers are unequal, then some transmitted data has probably been lostand a suitable error indication must be sent to the TIU or switchingunit which originated the data. For this purpose, conditional branchpoint 1249 passes control to block 1250. Block 1250 calls subroutineREQSIG which places the request for transmission of the signal withfunction code three and CH field eight to the TIU or switching unit withthe type 2 descriptor whose address is in T. After that call has beencompleted the packet buffer used to hold the incoming data packet mustbe returned to the common pool and for this purpose a call is made tosubroutine RELEASE SPACE as shown in block 1251. The address of thepacket buffer to be released is currently contained in temporary storagelocation B. After that, control passes back to the beginning of thelevel 2 sequence at conditional branch point 1241.

Returning now to conditional branch point 1249, it is seen that, if thesequence number contained in temporary location S is equal to thesix-bit number stored in RSEQ of the type 2 descriptor whose address iscontained in T, then control passes to block 1252. In block 1252temporary storage location S is increased by 1, modulo 64, and theresult is stored in field RSEQ of the type 2 descriptor addressed by T.In block 1253 the contents of field V.IN of the type 2 descriptoraddressed by T is increased by 1. In block 1254, the address of thesubchannel descriptor selected for data input is obtained from the fieldRSELCH in the type 2 descriptor addressed by T, and this subchanneldescriptor address is stored in temporary location C.

The type of data packet received is to be found in the least significanttwo bits of the field IDW in the packet buffer addressed by B. Block1255 is a computed branch point in which control is transferred to block1258 if the type of the data packet is zero, to block 1257 if the typeis equal to one, and to block 1256 if the type is equal to two. Thus,block 1256 is obeyed when the type of the incoming data packet equalstwo, indicating that it is the last packet in the message. The actiontaken in block 1256 is to call subroutine E.BURST.IN. This subroutineperforms the housekeeping associated with the end of an input burst.After that subroutine returns, control passes to block 1258. Block 1257is obeyed when the type of the incoming data packet is one, indicatingthat it is the last packet of a bundle. The action specified in block1257 is to call subroutine S.BUNDLE.IN which performs thestart-of-input-bundle housekeeping sequence on the subchannel addressedby C of the type 2 descriptor addressed by T. When that subroutinereturns, control transfers to block 1258.

The next action to be taken is to place the input data packet on thefirst-in-first-out queue of packets belonging to the subchanneladdressed by C and waiting for transmission on the next link of thesubchannel. The end of that queue is to be found in field DATAQT of thesubchannel descriptor addressed by C. The address of the queue entry iscopied in block 1258 to temporary location Q. The field TYPE in queueentry addressed by Q is then set equal to two if the type of theincoming data packet is also equal to two. That action is shown in block1259.

Conditional branch point 1260 then checks the type of the incoming datapacket and transfers control to block 1261 if it is the last packet of amessage. Otherwise it transfers to block 1262. The actions taken inthese two blocks are required to maintain in the field VOL of thesubchannel descriptor addressed by C a record of the volume of data heldin the first-in-first-out queue. For each packet added to the queue, a 1is added to the field VOL. In addition, for each end-of-message packetthe hexadecimal value $100 is added to field VOL. Whichever action takesplace, control then passes to block 1263, where the field DBLK in thequeue entry addressed by Q is set equal to the address contained inlocation B, which is the address of the incoming packet. In block 1264the field DATAQT in the subchannel descriptor addressed by C is updatedso that it points to the next unused entry in the queue. Specifically,it is set equal to the contents of the field NEXT in the queue entrypointed to by Q.

Conditional branch point 1265 then tests the field COSTAT in thesubchannel descriptor addressed by C. If that field is equal to two, thesubchannel is waiting fro sufficient data to be collected to justify thestart of a new output burst. Therefore, if COSTAT is equal to two,conditional branch point 1265 transfers control to block 1267 where acall is made to subroutine S.BURST.OUT which attempts to start a newoutput burst on the channel currently addressed by location C.

If the field COSTAT is not equal to two, then conditional branch point1265 transfers control to block 1266 where a call is made to subroutineREQOUT which places a request for attention in the data output attentionqueue associated with the type 1 descriptor associated with line or loopwhich the subchannel specified by C sends data. After obeying eitherblock 1267 or block 1266, control passes back to the beginning of thelevel 2 sequence of the data input, namely, to conditional branch point1241.

DATA OUTPUT ROUTINE OF THE CONTROL COMPUTER PROGRAM

Consider now the data output routine shown in FIGS. 21A and 21B. Thatroutine is obeyed entirely at level 1 and starts when line terminatingunit 31 is ready to take data packet from control computer 30. It isassumed that the data output routine is activated once every 250microseconds, that is, for every master frame time on the T1 line. Oneach occasion this routine is executed, it processes one entry on thedata output attention queue pointed to by field ATTNQ in the type 1descriptor pointed to by L. At the start of execution of the data outputroutine the field DXLAST in the type 1 descriptor pointed to by Lcontains the position of the entry processed during the last activationof the data output routine, so the first action taken by this routine isto update the field DXLAST so that it now points to the next queueentry. This is shown in block 1271. Since the queue is cyclic, occupyingconsecutive storage locations, it is necessary to increase the valuecontained in field DXLAST by 1, modulo the length of the queue.

Block 1272 uses the new value stored in field DXLAST as an index intothe data output attention queue whose address is contained in ATTNQ ofline descriptor addressed by L. The entry which this index gives isextracted from the list and copied into temporary location C. That entrywill either be 0 or the address of a subchannel descriptor requiringattention by the data output routine. Conditional branch point 1273tests to see which is the case and if it finds 0 transfers control tothe end of the data output routine at terminal indicator 1300.Otherwise, control passes to block 1274. As shown in block 1274, theentry in the list ATTNQ, from which the value now contained in temporarystorage location C was obtained, is set equal to 0.

When attention is requested on a subchannel, the field COSTAT in thesubchannel descriptor is set equal to 1. Conditional branch point 1275checks that this is true for the subchannel addressed by C, and, if itis not true, transfers control to the end of the data output routine atterminal indicator 1300. Otherwise, control passes to block 1276 wherethe field COSTAT in the subchannel descriptor pointed to by C isprovisionally set equal to 0, thereby indicating that the attentionrequest has been processed. The field SINK of the subchannel descriptorcontains the address of the type 2 descriptor relating to the TIU ortrunk to which data on that subchannel should be sent. The address ofthe type 2 descriptor is set in temporary location T as indicated inblock 1277. In fact, the field SINK in the subchannel descriptor is 0,if the subchannel requires the use of a trunk but has not yet beenassigned one.

Conditional branch point 1278 checks for this condition and transferscontrol to the end of the data output routtine at terminal indicator1300 if no trunk has been assigned. If T in fact contains the address ofthe type 2 descriptor, then control passes from conditional branch point1278 to conditional branch point 1279. At conditional branch point 1279a test is made on the field SSTAT, which is the output status for thetype 2 descriptor addressed by T. If that is non-zero then the terminalis not ready to output more data and conditional branch point 1279transfers control to the end of the data output routine at terminalindicator 1300. Otherwise, control passes to conditional branch point1280.

The first-in-first-out queue used to contain data packets waiting fortransmission on a subchannel is pointed to by the field NEXTOUTcontained in the subchannel descriptor. The last entry on that queue ispointed to by the field DATAQT of the subchannel descriptor. If thecontents of these two fields are the same then there is no data to beoutput. Conditional branch point 1280 checks for this condition and ifthere is no data, then control is transferred to the end of the dataoutput routine at terminal indicator 1300. Otherwise, control passes toblock 1281.

The address of the queue entry for the packet next to be output ispointed to by the field NEXTOUT in the channel descriptor addressed byC. That pointer is copied into temporary location B by block 1281 and inblock 1282 the field NEXTOUT is updated to point to the next queueentry, namely, the one pointed to by the field NEXT of the queue entrynow pointed to by the temporary location D. Having now decided to outputone more data packet, the data output routine adds one to the contentsof the field V.OUT in the type 2 descriptor addressed by T. That actionis taken in block 1283 shown in FIG. 21B.

If the new value of the field V.OUT is 0 then the packet must be thelast of a bundle. If that is the case, conditional branch point 1284transfers control to conditional branch point 1285, otherwise, controlis passed to block 1288. Even if V.OUT is equal to 0, the data packetmay be the last of a message. To test for this condition, the dataoutput routine examines the field TYPE in the queue entry addressed byB. If that field contains the value two then the data packet is indeedthe last of a message, and control is transferred from conditionalbranch point 1285 to block 1287. Otherwise, control passes to block1286.

Block 1286 sets the value 1 in temporary location F and block 1287 setsthe value two in temporary location F, and each then transfers controlto block 1292.

Turning attention now to block 1288, it is seen that this sets the valuetwo in temporary location F if the data packet is the last of a messagesince the field TYPE in the queue entry addressed by B will in thesecircumstances be equal to two. In all other circumstances it is 0.Conditional branch point 1289 now compares the field NEXTOUT and DATAQTin the subchannel descriptor addressed by C. If these fields are equal,then no more data is immediately available for output and control passesto conditional branch point 1291. Otherwise, control passes to block1290. The action specified in block 1290 is to place the subchanneladdressed by C into the data output attention queue belonging to thetype 1 descriptor addressed by L. The actions taken here are preciselythe same as those taken in subroutine REQOUT but in order to avoidtiming troubles block 1290 is a copy of the body of that subroutinerather than being a call to that subroutine.

In conditional branch point 1291 a check is made on the type of the datapacket being transmitted as stored in temporary location F. If that iszero, then it is not the last packet of a bundle or message and furthertransmissions are possible without the need to wait for anacknowledgment. When this is the case, control passes from conditionalbranch point 1291 to block 1293 where the field SSTAT in the type 2descriptor addressed by T is set equal to zero. After block 1293,control passes to block 1294. In the case where the type of the datapacket to be transmitted is non-zero, block 1292 is obeyed and there thefield SSTAT in the type 2 descriptor addressed by T is set equal to 1.That value indicates that further transmission cannot take place untilan ACK signal has been received. Control then passes to bloc, 1294.

As indicated in block 1294, the time at which data is transmitted isstored in the field STIME of the type 2 descriptor addressed by T. Thattime is obtained from storage location TIME where it is increased by 1once every 250 microseconds. Block 1295 computes the sequence number ofthe data packet to be transmitted. It does this by adding 1 to the fieldSSEQ contained in the type 2 descriptor addressed by T and this additionis done modulo 64 since the sequence number is a six-bit quantity.

The first word to be transmitted as part of the data packet contains theID of the TIU or trunk to which the packet is destined. The ID isobtained from the field ID in he type 2 descriptor addressed by T. Thesecond byte of the data packet contains the sequence number of thepacket in the most significant six bits and the type of the packet inthe least significant two bits. In this case the sequence number isobtained from the field SSEQ in the type 2 descriptor addressed by T andthe type of the packet is that value currently contained in temporarylocation F. As shown in block 1296, the first and second bytes of thedata packet are assembled to form a complete sixteen-bit word and storedin temporary location D.

Block 1297 shows that the sixteen-bit value is transferred from controlcomputer 30 to the line terminating unit 31 associated with the type 1descriptor whose address is L. The third byte from the data packet isthe length of data contained in the remaining part of the packet. Inthis case that length can be obtained from field DLENGTH in the packetbuffer addressed by the field DBLK of the queue entry addressed by B.The third byte of the data packet is an eight-bit checksum which is theEXCLUSIVE OR of the preceding three bytes.

In block 1298 it is shown that the third and fourth bytes, respectively,of the data packet are assembled into a sixteen-bit word and written outto the line terminating unit associated with the type 1 descriptorpointed to by L. Transmission of the remaining seventeen words of thedata packet is carried out autonomously using the aforementionedhigh-rate data transfer mechanism which is an integral part of the Tempo1 computer. In this case, the seventeen words are obtained from thefield BODY in the packet buffer addressed by the field DBLK which itselfis contained in the queue entry addressed by B. This autonomous transferis shown in block 1299, and once this transfer has been started, controlpasses immediately to the end of the data output routine at terminalindicator 1300.

SIGNAL INPUT ROUTINE OF THE CONTROL COMPUTER PROGRAM

The signal input routine is shown in FIGS. 22A-22F. That routine hassequences obeyed both at level 1 and at level 2. The sequence obeyed atlevel 1 starts at block 1310 in FIG. 22A and is obeyed when the lineterminating unit 31 has a signal packet available for collection bycontrol computer 30.

The level 1 sequence is used to transfer the contents of an incomingsignal packet into a queue of signal packets awaiting the attention ofthe level 2 sequence for signal input. The next available position inthat queue is pointed to by the field SRTAIL in the type 1 descriptorwhose address is L. Block 1311 shows that the address of this queueentry is copied into the temporary working location B. Next, block 1312shows that a sixteen-bit word is read from the line terminating unit 31associated with the type 1 descriptor addressed by L into the field FNof the queue entry addressed by B. In block 1313, the second word of theincoming signal packet is read from the same line terminating unit 31and placed in field CH of the queue entry addressed by temporarylocation B.

The fourth byte of a signal packet is always a checksum which is theEXCLUSIVE OR of the preceding three bytes. Therefore, by computing theEXCLUSIVE OR of all four bytes in the signal packet a result of 0 shouldbe obtained. That computation is shown in block 1314 and a test for the0 result is made in conditional branch point 1315. When a zero result isnot obtained, a transmission error has probably occurred and controlpasses from conditional branch point 1315 to the end of the signal inputroutine at terminal indicator 1324. Otherwise, control passes fromconditional branch point 1315 to block 1316. The first byte of thesignal packet contains the identification of the terminal interface unitor trunk to which that signal packet relates. For the signal packet justread, the identification byte can be found in the most significant eightbits of the field FN in the queue entry addressed by B. Block 1316 showsthat this identification field is transferred to the temporary storagelocation ID. When transmission is between a terminal interface unit anda switching unit, two different IDs are used, the difference betweentheir values being 128. The smaller value is used for transmissions outof the terminal interface unit into the switching unit and the largervalue is used for transmission out of the switching unit into thetherminal interface unit. There is no such convention for packetstransmitted between two switching units. Conditional branch points 1317and 1318 therefore provide a test for packets transmitted by a switcharound the transmission loop that is not being picked up by a terminalinterface unit and therefore have arrived at the switching unit.Conditional branch point 1317 transfers control around conditionalbranch point 1318 to block 1319 if the type 1 descriptor pointed to by Lis not a loop descriptor. That fact can be determined by looking for anegative value in the field TRLIST contained in the type 1 descriptoraddressed by L.

In the case where L is a loop, control passes to conditional branchpoint 1318 where a test is made on the identification currentlycontained in location ID. If that value is greater than 127 then thesignal packet is one that originated at the switch and has passedentirely around the loop and in that case control passes fromconditional branch point 1318 to the end of the signal input routine at1324. Otherwise, control passes to block 1319. The identification valuecontained in field ID is now used as an index into the list whoseaddress is contained in the field TERMINALS in the type 1 descriptoraddressed by L. Each entry in that list is the address of the type 2descriptor, and block 1319 shows that the address of the type 2descriptor which relates to the signal packet just read is transferredto temporary location T. If the entry in the list is 0 then theidentification code does not correspond to any existing TIU or trunk andconditional branch point 1320 will transfer control to the end of thesignal input routine at terminal indicator 1324. Otherwise, control willpass to block 1321.

The field TMNL in the queue entry addressed by B is now set by block1321 equal to the address of the type 2 descriptor currently stored inlocation T. The queue pointer contained in SRTAIL of the type 1descriptor L is now updated by block 1322 to contain the address of thenext available queue entry and that address can be obtained from thefield NEXT in the queue entry addressed by B. Having now stored detailsof the incoming signal packet in the signal input queue, an interrupt isset which will force level 2 action and subsequent processing by thelevel 2 sequence of the signal input routine. That interrupt is set byobeying an EDF instruction in the Tempo 1 computer. After block 1323,control passes to the end of the signal input routine level 1 atterminal indicator 1324.

The level 2 sequence for the signal input routine starts at terminalindicator 1330 as shown in FIG. 22B. At level 2, the signal inputroutine takes entries off the signal input queue which was loaded by thelevel 1 sequence of the signal input routine. The next entry to beprocessed on that queue is pointed out by the field SRHEAD contained inthe type 1 descriptor addressed by L. In block 1331 the address of thatqueue entry is transferred to temporary location B. If the addresscontained in SRHEAD is equal to the address contained in SRTAIL, thesignal input queue is in fact empty and conditional branch point 1332transfers control to the end of the signal input routine at terminalindicator 1333. Otherwise, control passes to block 1334.

The field TMNL in the queue entry addressed by B contains the address ofthe type 2 descriptor to which the input signal relates. That address istransferred in block 1334 to temporary location T. The action to betaken with respect to the incoming signal packet now depends upon thefunction code in that signal packet and whether a switching unit or TIUgenerated it. The field TRCHAIN in the type 2 descriptor addressed by Twill be less than 0 if the signal packet came from a terminal interfaceunit and will be positive if the signal packet came from anotherswitching unit. Conditional branch point 1335 tests to see which ofthese conditions exists and transfers control to computed branch point1336 if the source of the signal packet was a terminal interface unitand to computed branch point 1337 if the source was another switchingunit. Computed branch points 1336 and 1337 transfer control to variousdifferent places depending upon the function code in the signal packetjust read. That function code is in the least significant two bits ofthe field FN in the Q entry addressed by B.

The signal packet functions in the control transfers are as follows.First consider signal packets received from a terminal interface unit.Function code 0 identifies an ACK signal and results in control beingtransferred to conditional branch point 1337. Function code 1 identifiesan SEL signal and results in control being transferred to block 1361.Function codes two and three should not arise from the terminalinterface unit and are ignored by transferring control to the end of thelevel 2 processing sequence at terminal indicator block 1355. Nextconsider signal packets arriving from another switching unit. Functioncode 0 identifies an ACK signal and results in control being transferredto block 1375. Function code 1 identifies an STRT signal results incontrol being transferred to conditional branch point 1380. Functioncode two identifies an IDL signal and results in control being passed toblock 1390. Function code three identifies an NACK signal and results incontrol being passed to block 1393.

Considering now the process used to handle an ACK signal arriving fromterminal interface unit, the appropriate sequence begins at conditionalbranch point 1337. The third byte of that signal packet specifieswhether the terminal interface unit detected an error. That byte is tobe found in the CH field in the queue entry addressed by B. Conditionalbranch point 1337 checks its value. If non-zero, control is transferredto block 1393, otherwise control passes to block 1338. The mostsignificant six bits of the second byte in the signal packet contain thesequence number of the last packet correctly received by the terminalinterface unit. Since the second byte of the signal packet can currentlybe found in field FN of the queue entry addressed by B, block 1338transfers the sequence number from the most significant six bits of thatbyte into storage location S. For the acknowledgment to be meaningful,that sequence number should be equal to the sequence number of the lasttransmission by the switching unit as indicated in the field SSEQ of thetype 2 descriptor addressed by T.

Conditional branch point 1339 compares these two values and transferscontrol to the end of the level 2 signal input sequence at block 1335 ifthe sequence numbers are found to be unequal. Otherwise, control passeson to block 1340. The ACK signal acknowledges successful transmissionfrom the switching unit to the terminal interface unit and thattransmission relates to the subchannel addressed by field SSELCH in thetype 2 descriptor addressed by T. Block 1340 shows that the address ofthis subchannel descriptor is transferred into temporary storagelocation C. Computed branch point 1341 shows that the action now to betaken in response to the received ACK signal depends upon the status infield SSTAT of the type 2 descriptor addressed by T.

Status codes 0 and two require no further action on the part of thesignal input routine and control is transferred from computed branchpoint 1341 to the end of the level 2 sequence of block 1355. If thestatus is equal to 1, the ACK signal acknowledges the receipt of acomplete bundle of data and in this case control is passed to block1342. Status three indicates that the ACK signal acknowledges thereceipt of an SEL signal, and in that case control is transferred toblock 1360.

Returning now to the case where the ACK signal acknowledges receipt of abundle of data, it is seen that the signal input routine obeys theprogram sequence starting at block 1342 shown in FIG. 22C. The firsttask performed here is to examine the queue of the data blocks storedwith the subchannel addressed by C and to release the space of any datablocks whose transmission has now been acknowledged. During this processa marker is kept in temporary storage location E indicating whether ornot the acknowledged bundle of data contains the end of the message.That marker is initialized in block 1342 to zero.

Next, conditional branch point 1343 compares the address of the head ofthe queue contained in queue DATAQH with the value contained in fieldNEXTOUT of the same subchannel descriptor. If these two values areequal, then there is no data in the queue which was already beingtransmitted and in this case control passes from conditional branchpoint 1343 to conditional branch point 1349. If such data does existcontrol passes to block 1344.

The queue entry for the next block of data is extracted from fieldDATAQH in subchannel descriptor addressed by C and placed in temporarylocation B. In block 1345 it is seen that the field TYPE of the queueentry now addressed by location B contains the value two if the datapacket is the last of a message, and this value is transferred totemporary location E. The queue pointer DATAQH in the subchanneldescriptor addressed by C is updated to point to the next entry and theaddress of this next entry is to be found in field NEXT of the queueentry addressed by B. Block 1347 indicates that the RELEASE.SPACEsubroutine is called with the intnetion of returning to the commonsupply of storage space the packet buffer containing the data associatedwith the queue entry addressed by B. The address of that packet bufferis contained in field DBLK of the queue entry addressed by B. Block 1348then shows that the field VOL contained in the subchannel descriptoraddressed by C is reduced by 1. That field contains a count of thenumber of data blocks resident in the queue. Control is then transferredback to conditional branch point 1443 to test whether further queueentries must be processed. If no such entries remain, control istransferred from conditional branch point 1343 to conditional branchpoint 1349.

If the bundle of data now acknowledged was the last of a message, thentemporary location E will be non-zero and conditional branch point 1349will transfer control to block 1350. Otherwise, it will transfer controlto conditional branch point 1351. The field VOL in the subchanneldescriptor addressed by C has the hexidecimal value $100 added to it foreach message stored in the queue.

In block 1350 it is seen that the value contained in this field isreduced by hexidecimal $100. the end-of-message signals the end of aburst so control passes from block 1350 to block 1352 where a call ismade on the subroutine E.BURST.OUT which performs the necessaryhousekeeping associated with a burst of output on the subchanneladdressed by C of the type 2 descriptor addressed by T. After thisaction has been taken, control passes to block 1355. As was seen above,if the bundle acknowledged by the received ACK signal was not the lastbundle of a message then control passes to conditional branch point1351, at which point the field AOUT in the type 2 descriptor addressedby T is tested. When the terminal descriptor relates to a trunk, thatfield is 0. When the terminal descriptor relates to the terminalinterface unit, the field is 0 if the last bundle of an output burst hasbeen transmitted. In either case, the 0 value of this field will cause atransfer from conditional branch point 1351 to block 1352 and a non-zerovalue will cause a control transfer to block 1353.

It is seen in block 1353 that a call is made to subroutine S.BUNDLE.OUTwhich performs the necessary housekeeping associated with the start of anew output bundle on the subchannel descriptor addressed by C belongingto the type 2 descriptor addressed by T. Control is next transferred toblock 1354 where a call is made on the subroutine REQOUT for the purposeof requesting attention by the data output routine. An entry giving theaddress of the subchannel descriptor pointed to by C is made in the dataoutput attention queue for the data output routine and control istransferred to block 1355.

Block 1355 is obeyed when one signal obtained from the signal inputqueue has been processed. That signal will still be the topmost entry inthe queue and will be addressed by the field SRHEAD in the type 1descriptor addressed by L. To remove that entry from the queue, thefield SRHEAD is updated by placing in it the contents of field NEXT inthe queue entry being removed. After doing this, control passes to block1331 where an attempt is made to process other entries in the signalinput queue.

Considering now the case when the received ACK signal acknowledges thereceipt of and SEL signal, it was seen that computed branch point 1341transferred control to block 1360. The action described in block 1360shown in FIG. 22D is to call subroutine S.BURST.OUT which performs thehousekeeping associated with the start of the new burst of data outputon the subchannel descriptor addressed by C. After that subroutinereturns, control passes to block 1355.

Consider now the processing of an SEL signal received from the terminalinterface unit. As described above, computed branch point 1336 will inthis case transfer control to block 1361. SEL signals, like datapackets, are sequentially numbered and the sequence number is in themost significant six bits of the second byte of the packet of the signalpacket just received. The second byte is contained in the mostsignificant eight bits of the field FN in the queue entry addressed byB.

Block 1361 indicates that the sequence number from this byte istransferred to temporary location S. That sequence number should matchthe number contained in the field RSEQ held in the type 2 descriptoraddressed by T. If that is not the case, then some data transmission hasprobably been lost.

Conditional branch point 1362 makes a comparison and arranges to ignorethe signal if an error is detected by transferring control to block1355. If the sequence numbers are equal, control is passed to block 1364where the sequence number of the next packet expected is computed. Thatsequence number is one greater than the number of the current packet,but since the sequence number is a six-bit quantity the addition is donemodulo 64. In block 1364 the new sequence number is stored in field RSEQof the type 2 descriptor addressed by T. In block 1365 the time at whichthe signal was processed is stored in the field RTIME in the type 2descriptor addressed by T. Next, block 1366 calls subroutine E.BURST.INwhich performs the housekeeping associated with the end of a burst ofdata input from the trunk or TIU whose descriptor is addressed by T.

The third byte of an SEL signal packet contains the number of a channelwhich is about to be selected. That number can be obtained from the mostsignificant byte in the field CH of the queue entry addressed by B. Asshown in block 1367, the new channel number is transferred to temporarylocation N. The next action to be taken is to search the list ofchannels associated with the type 2 descriptor addressed by T to findthe channel which has the appropriate number. As will be seen later,this sequence is used also by the STRT signal. The sequence starts withblock 1368 which obtains from the field channels in the type 2descriptor addressed by T the address of the first subchannel descriptorassociated with that channel. Conditional branch point 1369 checks tosee if the address contained in temporary location C is 0. If it is,then no channel exists and the SEL signal is ignored by transferringcontrol to block 1355. If temporary location C indeed contains theaddress of the subchannel, then conditional branch point 1370 shows thatthe channel number stored in temporary location N is compared with thechannel number stored in the subchannel descriptor field CHANNO. Ifthese two numbers are equal, then the requiredchannel has been found andcontrol is passed to block 1371. Otherwise, the search must continue andcontrol is passed to block 1372.

From block 1372 it is seen that the field NEXT in the subchanneldescriptor addressed by C is used to obtain the address of the nextsubchannel descriptor to be inspected. That address is copied intolocation C and control is transferred back to conditional branch point1369. The subchannel descriptors which are chained from a type 2descriptor T are all those subchannels whose data output is destined forthat TIU or trunk. The descriptors of the subchannels which handle thedata input from that TIU or trunk are adjacent in the store to thesubchannel descriptors listed. The address of the descriptor for thesubchannel handling data input from TIU or trunk T can be computed by anEXCLUSIVE OR operation on the address currently contained in location C.In block 1371 it is seen that this computation is made and the resultingvalue of C is stored in the field RSELCH of the type 2 descriptorassociated with T. By taking this action, subsequent data input fromthat TIU or trunk will be directed to the subchannel addressed by C. Inblock 1373 it is seen that the field N.IN in the type 2 descriptoraddressed by T is set equal to the field NAX.N in the subchanneldescriptor addressed by C. Then in block 1374 it is seen that a call ismade to subroutine S.BURST.IN which performs the housekeeping associatedwith the start of a burst of input data on the subchannel addressed by Cfrom the TIU or trunk whose descriptor is addressed by T. After the callhas been completed control is transferred to block 1355.

Next to be considered in an ACK signal arriving from another switchingunit. It will be seen in the discussion of block 1337 that when such asignal arrives control is transferred to block 1375 shown in FIG. 22E.The most significant six bits of the second byte in that signal packetcontain the sequence number which is the number of the last packetsuccessfully received by the other switching unit. The second byte ofthe signal packet is in the most significant eight bits of the field FNin the queue entry addressed by B.

Block 1375 shows that the sequence number from that byte is transferredto temporary location S. In conditional branch point 1376 a comparisonis made between the receive sequence number and the value stored in SSEQof the type 2 descriptor addressed by T. If these two values are notequal, then the incoming ACK signal is ignored by transferring controlto block 1355.

The incoming ACK signal is also ignored if the status SSTAT stored withthe type 2 descriptor addressed by T is equal to neither one nor three.A test of this effect is made by conditional branch points 1377 and1378. If neither of these values is to be found in field SSTAT thencontrol is transferred by conditinal branch point 1378 to block 1355.Otherwise, control passes on to block 1379.

The incoming ACK signal from another switching unit contains in itsthird byte a sequence number which determines the length of the nextburst that can be transmitted to that switching unit. The length of thatburst is computed in block 1379. Since the third byte of the signalpacket can be found in the most significant byte of field CH in thequeue entry addressed B, the length of the next burst is the differencebetween this value and the sequence number stored in SSEQ of the type 2descriptor addressed by T. As seen in block 1379, the length of thatburst is stored in location V.OUT of the type 2 descriptor associatedwith T, and control is then transferred to block 1340. It will berecalled that the sequence containing block 1340 is used to handle anACK signal coming from the terminal interface unit and is in factequally applicable to an ACK signal coming in from another switchingunit.

Turning again to computed branch point 1337, it is seen that an STRTsignal with a function code of one results in a control transfer toconditional branch point 1380. The purpose of that signal is to indicatethat a trunk has been assigned for the purpose of sending data into theswitching unit receiving the STRT signal. The subchannel to which thetrunk has been assigned is identified by a fourteen-bit numberconstructed from the most significant six bits in the second byte of thesignal packet and the eight bits in the third byte of the signal packet.The action taken in block 1380 is to compute that number and store it intemporary location N.

Conditional branch point 1381 then checks the status of the type 2descriptor addressed by T as stored in the field RSTAT. A status valueof three here indicates that the trunk was marked as "idle" and in thiscase control transfers from conditional branch point 1381 to block 1385.In the case where the trunk is not idle, it is necessary to check to seewhether the STRT is a duplicate of one received earlier or whether thetype 2 descriptor was not updated when the trunk was released. For thispurpose, block 1382 computes the address of the subchannel descriptorcontaining the number of the subchanels to which input data from thetrunk is currently assigned. The address of the descriptor for thatsubchannel is contained in field RSELCH in the type 2 descriptoraddressed by T. Conditional branch point 1383 then compares the numberspecified in the STRT signal with the channel number of the subchannelcurrently being used for data input from the trunk. If these are equal,the STRT signal is a duplicate of one received earlier and no processingis necessary. Control is therefore transferred to block 1355. If thevalues are unequal, the trunk was not properly released and that actionis now taken in block 1384. To release the trunk a call is made tosubroutine E.BURST.IN which performs all housekeeping associated withthe end of an input burst from the trunk whose type 2 descriptor isaddressed by T. After that action has been taken control is transferredto block 1385.

The sequence number of the first packet expected on the newly assignedtrunk will be one greater than the sequence number currently containedin field RSEQ of the type 2 descriptor addressed by T. Block 1385computes the new sequence number modulo 64 and stores it in the fieldRSEQ. Block 1386 copies the current time from the location TIME into thefield RTIME in the type 2 descriptor addressed by T. the remainingaction taken with respect to the STRT signal parallels that taken forthe SEL signal. In particular, it is necessary to search through thelist of channels for one with the appropriate number.

However, in the case of the STRT signal, the list of channels is pointedto by the field CHLIST in the type 1 descriptor addressed by L. Thus,block 1387 obtains the address of this list and stores it in temporarylocation C before transferring control into the middle of the sequencepreviously described to handle SEL signals. Control is then transferredto conditional branch point 1369.

An IDL signal received from the switching unit has function code two andcauses a control transfer from computed branch point 1337 to block 1390shown in FIG. 22F. The IDL signifies the release of a trunk and thesequence number in the most significant six bits of the second byte ofthe signal packet specify the number to be used when the trunk is nextused. In block 1390 the sequence number is obtained from the mostsignificant bits of the byte in the least significant position of thefield FN in queue entry B, and that sequence number is stored in thefield RSEQ of the type 2 descriptor addressed by T. To disassociate thetrunk with the subchannel to which it is linked, the signal inputroutine calls upon the subroutine E.BURST.IN as shown in block 1391.This subroutine performs the necessary housekeeping associated with theend of an input burst from the TIU or trunk whose descriptor isaddressed by T. Finally, the trunk is marked as "idle" by setting thefield RSTAT in the type 2 descriptor addressed by T equal to three, andthen control is transferred to block 1355.

Block 1393 is obeyed on two accounts. In the first instance it is obeyedwhen an NACK signal is received from another switching unit, and in thiscase computed branch point 1337 transfers control directly to block1393. Alternatively, block 1393 computes when an ACK signal is receivedfrom a terminal interface unit and when that ACK signal indicates thaterrors were detected by the terminal interface unit. As was describedearlier, this situation prompts the transfer of control from conditionalbranch point 1337 directly to block 1393. The action taken in block 1393is to call the subroutine RETREAT which steps back the queue pointersand associated controls for the subchannel currently transmitting datato the TIU or trunk whose descriptor is addressed by T. The distance ofbacktrack is determined by a sequence number known internally to theroutine as S₈. That sequence number must be the number of the lastpacket successfully transmitted and received. That number is to be foundin the most significant six bits of the second byte of the signal packetcurrently located in the least significant byte point of the field FN inthe queue entry whose address is B. Subroutine RETREAT takes specialaction in respect of error code eight which is used by the terminalinterface unit to indicate that data or select signals are being sent ona channel which is not the same as the one being used for datatransmission. The temporary working location W₈ , used by subroutineRETREAT is set non-zero if that particular error condition exists. Aftercompletion of the call shown in block 1393, control is transferred tothe end of the signal processing sequence of block 1355.

SIGNAL OUTPUT ROUTINE OF THE CONTROL COMPUTER PROGRAM

The signal output routine is illustrated in FIGS. 23A and 23B. It isseen that that routine is obeyed entirely at level 1 and starts at block1400 shown in FIG. 23A when the line terminating unit with type 1descriptor addressed by L is ready to take another signal packet. Theroutine services a queue built up by subroutine REQSIG. The head of thatqueue is contained in the field SXHEAD in the type 1 descriptoraddressed by L. The action described in block 1401 is to transfer theaddress of the head of that queue into temporary location B. If thevalue in SXHEAD is equal to the value in SXTAIL, then the queue is emptyand conditional branch point 1402 transfers control to the end of thesignal output routine at terminal indicator 1407A. Otherwise, itproceeds to process that queue entry by passing control to block 1403.The address of the type 2 descriptor to which the signal output requestrelates is contained in the field TMNL in the queue entry addressed byB. As shown in block 1403, the address of that type 2 descriptor istransferred to temporary location T.

The action to be taken with respect to the signal being transmitteddepends on the function code of that signal. The function code iscontained in the least significant two bits of the field FN in the queueentry addressed by B. Computed branch point 1404 transfers control toblock 1408 in the case where an ACK signal with function code zero isrequested; it transfers control to block 1412 in the case where an SELor STRT signal with function code one is requested; and otherwisetransfers control to block 1405.

Considering now the transmission of packets with function codes two andthree, these are handled by the sequence starting at block 1405. Thefirst byte in each packet is the identity of the thermal interface unitor trunk to which that signal relates and can be obtained from the fieldID in the type 2 descriptor addressed by T. The second byte in thesignal packet has in its most significant six bits the sequence numbercurrently contained in the field SSEQ of the type 2 descriptor addressedby T, and has in its least significant two bits the function codecurrently contained in the least significant two bits of the field FN inthe queue entry addressed by B. Block 1405 shows that these values areassembled into a complete word stored in temporary location D. This wordis written by the control computer 30 into the line terminating unit 31associated with the type 1 descriptor addressed by L as shown in block1406. The third byte of the signal packet is equal to that valuecurrently contained in the field CH of the queue entry addressed by B,and the fourth byte is a checksum being the EXCLUSIVE OR of the valuesin the first three bytes. Block 1407 shows that the second and thirdbytes are assembled into a word which is then written out to the sameline terminating unit. Control then is transferred to the end of thesignal output routine at terminal indicator 1407A.

Consider now the case when an ACK signal is transmitted. As was seenabove, control in this case will be transferred from computed branchpoint 1404 to block 1408. The first byte to be transmitted in the signalpacket is equal to the identity of the terminal interface unit or trunkwith which the signal is associated and that value is obtained fromfield ID in the type 2 descriptor addressed by T. The second byte of thesignal packet has in its most significant six bits the value containedin field RSEQ of the type 2 descriptor addressed by T, and in the leastsignificant two bits it has zero.

Block 1408 explains what these two bytes are assembled together into aword and stored in temporary location D. That value is written into theline terminating unit 31 associated with type 1 descriptor addressed byline L as shown in block 1409. The third byte of an ACK signal mustspecify the sequence number to be used at the end of the next burst oftransmission. The sequence number currently held in RSEQ of the type 2descriptor addressed by T is that for the last transmission received.Furthermore, the values stored in field V.IN of the type 2 decriptoraddressed by T is minus one times the number of packets which areauthorized for transmission in the next burst. Therefore, by subractingV.IN from RSEQ, the sequence number to be used at the end of the nextburst of transmission is obtained. Block 1410 shows that this number isstored in temporary location V. The third byte of the signal packet is achecksum being the EXCLUSIVE OR of the preceding three bytes. Block 1411shows that the second word of the signal packet is assembled from thevalues stored in temporary location V on the computed checksum. Thisvalue is written to the line terminating unit associated with L. Controlthen transfers to the end of the signal output routine at terminalindicator 1407A.

Computed branch point 1404 transfers control to block 1412 shown inFIGS. 23B when the request is made to transmit either an SEL signal oran STRT signal, both of which have the function code of one. In eachcase the sequence number held in SSEQ of the type 2 descriptor addressedby T is increased by one before the transmission takes place. Thatcomputation is made modulo 64 since the sequence number is a six-bitquantity. The value contained in the most significant six bits of thesecond byte of the signal packet depends upon whether that packet is anSEL signal or an STRT signal. If the signal is being sent on a trunkthen it is an STRT signal, otherwise it is an SEL signal. Adetermination to this effect can be made by testing the field SRCHAIN inthe type 2 descriptor addressed by T. That field is negative if what itrelates to is a terminal interface unit, and positive if it relates to atrunk.

Control passes from control point 1413 to block 1415 when an SEL signalis being transmitted, and block 1415 then obtained the sequence numberfrom the field SSEQ of the type 2 descriptor which is addressed by T,storing that number in temporary location S. When the signal is an STRTsignal, the most significant six bits of the fourteen-bit channel numbercontained in the field SELNO of type 2 descriptor addressed by T, areextracted and stored in temporary location S, as shown in block 1414.

After execution of either block 1414 or block 1415, contro passes toblock 1416 where the first word of the signal packet is assembled. Thefirst byte of that packet is the terminal identity obtained from thefield ID of the type 2 descriptor addressed by T. The second byte ofthat packet has in its most significant six bits the value currentlycontained in temporary location S and has 1 as the function code in itsleast significant two bits. As shown in block 1417, the assembled wordwhich was stored in temporary location D is now output to the lineterminating unit. The third byte of a signal packet is obtained from theleast significant eight bits of the channel number held in the fieldSELNO of the type 2 descriptor addressed by T. As shown in block 1418,that value is transferred into temporary location S. The fourth byte ofthe signal packet is a checksum being the EXCLUSIVE OR of the precedingthree bytes. It is shown in block 1419 that the second and third bytesare assembled and written to the line transmit unit associated with thetype 1 descriptor addressed by L. Finally, control is transferred to theend of the signal output routine at terminal indicator 1407A.

TIME-OUT ROUTINE OF THE CONTROL COMPUTER PROGRAM

FIGS. 24A and 24B show the time-out routine which is obeyed entirely atlevel 2 and is called once every two milliseconds. The function of thisroutine is primarily to detect when transmission has come to a halt dueto the loss of the signal or failure to queue an output request whenappropriate. Once every two milliseconds the routine inspects one type 2descriptor of the many type 2 descriptors held in the system. All theseterminal descriptors are linked together by the field NEXT and from acircular chain. The storage location SCANNED contains the address of theterminal descriptor processed in the last activation of the time-outroutine. In block 1421 it is seen that the first act is to put into thelocation SCANNED the address of the next type 2 descriptor in the cyclicchain. The address of the type 2 descriptor now to be inspected iscopied into temporary location T as shown in block 1422. The address ofthe descriptor of the subchannel currently associated with that terminalfor data input is copied into temporary location C from field RSELCH inthe type 2 descriptor addressed by T. The action now taken depends uponthe status of the TIU or trunk as stored in the field RSTAT in the type2 descriptor addressed by T. A status value of three calls for noparticular action and control is transferred to computed branch point1428. If the status value is two, control is transferred to block 1430,and if the status is 1, control is transferred to block 1431. In thecase when the status is 0, normal data transmission is in progress andthe routine proceeds to obey the conditional branch point 1425. At thatbranch a test is made on the field RTIME in the type 2 descriptoraddressed by T. That field contains the time when the last transmissionfrom the terminal was received, which is compared with the time storedin the location TIME. If the absolute value of the difference betweenthese two values is greater than 2000, indicating that about half asecond has elapsed since any transmission from the TIU or trunk wasreceived, then control passes to block 1426. Otherwise, no action istaken and control passes to computed branch point 1428. It is seen inblock 1426 that field RTIME is set equal to the current value of timeand that in block 1427 a request for a signal output is made by callingsubroutine REQSIG. That subroutine asks for the output of an ACK signalto be sent to the TIU or trunk whose descriptor is addressed by T. Whenthe call is completed, control passes to computed branch point 1428.

In the case where the status value held in RSTAT is equal to 1, computedbranch point 1424 transfers control to block 1431. That status valueindicates that the TIU or trunk is waiting for space in order to be ableto start the new bundle of input data transmission. A second attempt tostart the bundle is made as shown in block 1431 by calling subroutinesS.BUNDLE.IN. This performs the necessary housekeeping associated withthe start of an input bundle from the TIU or trunk whose descriptor isaddressed by T on the subchannel whose descriptor is addressed by C.Once this call has been completed, control is transferred to computedbranch point 1428. In the case where the status value held in fieldRSTAT is a two, control passes from computed branch point 1424 to block1430. That status value indicates that the TIU or trunk is waiting for atrunk in order to start an input burst. A second attempt to start theburst is made by calling on the subroutine S.BURST.IN as shown in block1430. That subroutine performs all the necessary housekeeping associatedwith the start of an input burst from the TIU or trunk whose descriptoraddress is in T on the subchannel whose address is in C. After the callhas been completed, control is transferred to computed branch point1428.

Considering now the sequence starting at computed branch point 1428, thetime-out routine extending the status of the TIV or trunk with respectto data transmission out of the switching unit. That status is stored inlocation SSTAT in the type 2 descriptor addressed by T. Computed branchpoint 1428 transfers control to various points depending upon the valueof the status. The status value 0 results in a transfer to block 1429;status value one results in a transfer to conditional branch point 1432;status value two results in a transfer to block 1435; status value threeresults in a transfer to conditional branch point 1432; and status valuefour results in a transfer to block 1443.

Considering now the sequence beginning at block 1429 which is obeyedwhen status value 0 indicates that normal transmission activity is inprogress. In this case the time-out routine calls subroutine S.BURST.OUTwhich is designed to have no effect unless the terminal is unnecessarilyidle and to attempt to start a burst if that is the case. The subroutineperforms its housekeeping with respect to the channel descriptor whoseaddress can be obtained from the field SSELCH whose type 2 descriptor isaddressed by T. After completing the call, control transfers to the endof the time-out routine at terminal indicator 1444. Returning tocomputed branch point 1428, when the status field SSTAT contains eithervalue 1 or value three, it indicates that the switching unit is waitingfor an ACK signal to arrive from a TIU or other switching unit. In thesecircumstances, control is transferred to conditional branch point 1432shown in FIG. 24B.

First in the sequence a check is made on the field STIME in the type 2descriptor addressed by T. That field is compared with the current valueof time and if the absolute value of the difference between these twovalues is not greater than fifty no action is taken and control passesto the end of the time-out routine at terminal indicator 1444. In thecase when the time difference is greater than fifty, action is taken bypassing control to block 1433.

First, the field STIME is set equal to the current time as shown inblock 1433, then a call is made to subroutine RETREAT. This subroutinebacks up the output queue and associated controls, thereby enablingre-transmission to the TIV or trunk of the most recently transmittedinformation. The sequence number which the RETREAT subroutine requiresis a specification for the distance of backup and is computed to be oneless modulo 64 than the current value in field SSEQ of the type 2descriptor addressed by T. After completion of the call control istransferred to the end of the time-out routine at terminal indicator1444.

Returning again to computed branch point 1428, control is transferred toblock 1435 if the status value in SSTAT is two. That status indicatesthat insufficient data has been collected on any channel which can beselected so, in fact, no channel at all has been selected for dataoutput. The sequence beginning at block 1435 attempts to verify thissituation and to find the channel which can be selected if thatsituation is in fact not the case.

First in that sequence, the address of the subchannel selected for datainput from the TIU whose descriptor address is T is obtained from fieldRSELCH. That subchannel is one of a pair, the other subchannel carryingdata in the opposite direction, that is, towards the TIU whosedescriptor address is T. The address of the descriptor for the othersubchannel is obtained by an EXCLUSIVE OR with value sixteen. It isshown in block 1435 that the address of the descriptor for that otherchannel is stored in temporary location N.

Next the time-out routine scans the list of channels for the TIU whosedescriptor address is T. As shown in block 1436, the head of this listis copied into temporary location C. Conditional branch point 1437checks to see of C is zero, and if it is, transfers control to the endof the time-out routine at terminal indicator 1444. Otherwise, controlpasses to conditional branch point 1438. If the field COSTAT of thechannel descriptor whose address is C is less than two, then it hassufficient data to warrant the start of a new burst of transmission andconditional branch point 1438 transfers control to clock 1442. If thefield COSTAT of the subchannel whose address is C contains the value twothen sufficient data is not available and control is transferred toblock 1441. Otherwise, COSTAT is equal to three, indicating thatsufficient data exists but the channel was rejected as a suitablechannel for selection by the TIU. In this case control passes toconditional branch point 1440.

If the address of the channel descriptor equals the address contained intemporary location N, then it is probable that the TIU will be preparedto select this channel so an attempt is made to start a new burst onthat channel by transferring control to block 1442. If this is not thecase control passes to block 1441 where the time-out routine moves downthe chain of channel descriptors for TIU T. The field next in eachsubchannel descriptor contains the address of the next subchanneldescriptor as shown in block 1441. Block 1441 passes control back to thebeginning of the scanning loop branch point 1437. Block 1442 is obeyedwhen it is determined that a burst of transmission might be started tooutput the data currently stored in the subchannel whoseaddress isstored in C. As shown in block 1442 a call is made to subroutineS.BURST.OUT. This subroutine performs the necessary housekeepingassociated with the start of a new burst of output on the channel whosedescriptor address is contained in C. On completion of the call controlis transferred to the end of the time-out routine at terminal indicator1444.

Control is transferred to block 1443 when the field SSTAT of a trunkdescription contains the value four, indicating that the trunk is idle.Block 1443 calls subroutine SIGOUT which requests that an IDLE be sentto the switching unit at the other end of the trunk. When the subroutinereturns, the time-out routine ends at terminal indicator 1444.

S.BURST.IN SUBROUTINE OF THE CONTROL COMPUTER PROGRAM

FIG. 15A shows the subroutine S.BURST.IN whose function is to performthe housekeeping associated with the start of a new input burst. Onentry it requires two parameters. Parameter C13 contains the address ofa subchannel descriptor, and parameter T13 contains the address of theassociated type 2 descriptor. The subroutine begins at terminalindicator 1450. Under normal operating conditions, field SINK in thesubchannel descriptor contains the address of the type 2 descriptorassociated with that subchannel. In the case when the subchannel wouldnormally use a trunk but at the current time is inactive, the field SINKcontains zero. Conditional branch point 1451 tests this field or thesubchannel descriptor whose address is in C13 and transfers control toblock 1453 if the field is non-zero. Otherwise, it transfers control toblock 1452 for the purpose of finding a trunk to that subchannel. Asshown in block 1452 the assignment is done by calling the subroutineASSIGN.TRUNK which uses as parameters the address of the subchanneldescriptor contained in C13 and the address of the type 2 descriptorcontained in T13. That subroutine has two exits. A success exit us usedif the trunk was successfully assigned and a fail exit if no trunk wasobtained at that time. Control passes from the success exit to block1453 and from the fail exit to block 1456.

Assuming then that the assignment to the trunk was successful, block1453 sets field CRSTAT in the subchannel descriptor addressed by C13equal to 0. Then block 1454 calls upon the subroutine S.BUNDLE.IN toperform the housekeeping necessary to initiate the input of a newbundle. Parameters for that subroutine are the subchannel addresscurrently contained in C13 and the type 2 descriptor address currentlycontained in T13. After completion of the cell, control passes to theend of the subroutine at terminal indicator 1455.

Returning now to consider the fail exit from block 1452, control passesfrom this to block 1456 where the field RSTAT in the type 2 descriptorwhose address is contained in T13 is set equal to two. That numberindicates that the terminal wishing to start a new input burst must waituntil the trunk becomes available. Block 1457 is a call to subroutineREQSIG which in this case is requester to output an ACK signal to theTIU or trunk that would have started a new input burst. Since notransmission has yet been authorized, the ACK signal would instruct theTIU or trunk not to transmit any further data. Following from block1457, block 1458 sets the field CRSTAT in the type 2 descriptor whoseaddress is in T13 equal to one, indicating thereby that burst input isnot in progress. Control then passes to the end of the subroutine interminal indicator 1455.

E.BURST.IN SUBROUTINE OF THE CONTROL COMPUTER PROGRAM

FIG. 25B shows the subroutine E.BURST.IN which is used to perform thehousekeeping function associated with the termination of an input burst.The single parameter required by the subroutine is the address of a type2 descriptor. This address must be in working location T1. The routinebegins in terminal indicator 1460. When an input burst terminates, anyunused space assignment must be returned to the common pool. The volumeof space involved here is obtained by subtracting V.IN from A.IN in thetype 2 descriptor addressed by T1. That computation is shown in block1461 and the result is stored in temporary location N1. In block 1462the value contained in N1 is added to the value contained in the storagelocation UNASSIGNED SPACE and the result is put back in the storagelocation UNASSIGNED SPACE. In block 1463 it is seen that the field A.INand the field V.IN in the type 2 descriptor addressed by T1 are both setequal to 0.

Block 1464 shows a call to subroutine REQSIG whose function is torequest that the signal output routine send an ACK signal to a TIU ortrunk whose decriptor address is contained in T1. Control then passes toblock 1465 where the field CRSTAT in the type 2 descriptor whose addressis T1 is set equal to 1 indicating that burst transmission is no longerin progress, and control passes to the end of the subroutine at terminalindicator 1466.

S.BUNDLE.IN SUBROUTINE OF THE CONTROL COMPUTER PROGRAM

FIG. 25C shows the subroutine S.BUNDLE.IN whose function is to performthe housekeeping associated with the start of a new input bundle. Theinput parameters required by this routine are C2, the address of asubchannel descriptor and T2, the address of its associated type 2descriptor.

The routine begins at terminal indicator 1470. Cince no data can be readfrom the input line or loop until storage space is available to hold it,bundle transmission cannot start unless sufficient storage space hasbeen assigned. Field A.IN in the type 2 descriptor addressed by T2contains the number of blocks of storage which have currently beenassigned to TIU or trunk T2 but have so far been unused. If A.IN is 0,then more space must be requested. Conditional branch point 1471 testsfor this situation and, if space does remain, turns over control toblock 1473. Otherwise, control passes to block 1472 where a call toASSIGN.SPACE subroutine is made. Parameters for the space assignmentsubroutine are the subchannel address C2 and the address of theassociated type 2 descriptor T2. The assigned space subroutine can exitin two ways. A success exit is used if space was successfully required,and a fail exit if not. Upon a success exit from block 1472, controlpasses to block 1473, and upon a fail exit control passes to block 1476.

Assuming now that the assignment of space was successful, block 1473computes the maximum allowable size for the next bundle. That size isthe smaller of the two values contained in N.IN and A.IN of the type 2descriptor whose address is in T2. The computed result is deposited intemporary location N2. Field V.IN of the TIU or trunk descriptorcontains munus one times the number of packets authorized fortransmission in the next bundle. Therefore, in block 1474 it is seenthat the field V.IN of a type 2 descriptor whose address is in T2 is setequal to minus the value currently found in N2. Then in block 1475 thevalue currently held in field A.IN of the type 2 descriptor addressed byT2 is reduced by the amount contained in N2. Control then passes toblock 1476 where a request is made to send an ACK signal to the TIU ortrunk associated with the descriptor with the address T2. For thispurpose the subroutine REQSIG is used. Upon completion of the call tothat subroutine, control passes to the end of the S.BUNDLE.IN subroutineat terminal indicator 1477.

S.BURST.OUT SUBROUTINE OF THE CONTROL COMPUTER PROGRAM

FIG. 25D shows the subroutine S.BURST.OUT which handles the housekeepingassociated with the start of a new burst of output transmission. Thesingle parameter required by this routine is C3, the address of asubchannel descriptor.

The subroutine begins in terminal indicator 1480. The field SINK of asubchannel contains the address of the descriptor which relates to theTIU or trunk to which data is being sent. It is seen in block 1481 thatthe address of the type 2 descriptor is stored in temporary location T3.Conditional branch point 1482 then tests the field TRCHAIN which isfound in the type 2 descriptor addressed by T3. It does this in order todetermine whether the descriptor is that of a trunk or a terminalinterface unit. The field TRCHAIN will be negative if the descriptorrelates to a terminal interface unit and in that case control will passthrough conditional branch point 1482 to conditional branch point 1491.In the case where T3 relates to a trunk, control passes to conditionalbranch point 1483. The test on field COSTAT in the channel descriptoraddress by C3 and shown in conditional branch point 1483 is made inorder to determine whether an output request is already outstanding forthis subchannel. In that case control passes from conditional branchpoint 1483 to the end of the subroutine at terminal indicator 1487,otherwise control passes to conditional branch point 1484.

The next test which is made is in conditional branch point 1484 andseeks to determine whether there is any data at all in the subchannelC3. The field VOL in the descriptor for that subchannel will be 0 if thedata output queue is empty and in that case conditional branch point1484 will transfer control to conditional branch point 1485. When datadoes exist in the output queue of C3, control passes to block 1488.Assuming now that the output queue is empty, a test is made on the fieldCRSTAT in the subchannel descriptor addressed by C3. That field will be0 if there is an active burst transmission of data into the subchannelC3, otherwise it will be non-zero. If indeed there is active bursttransmission, control passes to the end of the routine at terminalindicator 1487. Otherwise, control passes to block 1486 for the purposeof releasing the trunk which subchannel C3 has assigned to it. As isshown in block 1486, the trunk is released by using the subroutineRELEASE.TRUNK and by providing it with the subchannel descriptor addressC3 and the type 2 descriptor address T3. After releasing the trunkcontrol passes to the end of the routine at terminal indicator 1487.

Turning now to block 1488 where control passes if there is datacollected in the subchannel C3, it is seen that the first two actionstaken are to clear the fields COSTAT in the channel descriptor and SSTATin the type 2 descriptor. Control then passes on to block 1490 where arequest is made for the purpose of sending an ACK signal to the TIU ortrunk associated with T3. To effect this request, the subroutine REQOUTis used. Following completion of the request, control passes to the endof the subroutine at terminal indicator 1487.

As was seen above, control passes from conditional branch point 1482 toconditional branch point 1491, if the type 2 descriptor whose address iscontained in T3 described a terminal interface unit. The sequence whichbegings in block 1491 seeks to determine whether subchannel C3 should beselected for the purpose of sending a new burst of data to TIU T3. Thatquestion only arises when subchannel C3 is not currently selected forburst transmission to TIU T3 and the status is indicated by the contentsof field SSTAT in the TIU descriptor. If that field contains value two,then conditional branch point 1491 will transfer control to block 1492.Otherwise, it will skip around the channel selection sequence to block1497.

A status value of two indicates that no channel is currently selected asbeing suitable for burst transmission, presumably because no channelcontains a sufficient volume of data to justify the start oftransmission.

On the assumption that subchannel C3 does in fact justify the start ofburst transmission, block 1492 sets the field SSELCH in the TIUdescriptor T3 equal to the address of the subchannel descriptorcontained in C3. Then block 1493 extracts the channel number for thatsubchannel from field CHANNO in the subchannel descriptor and puts thenumber in field SELNO, the TIU descriptor addressed by T3. Control thenpasses on to conditional branch point 1494. AT that pont a test is madeon the field COSTAT in the subchannel descriptor addressed by C3. Ifthat field contains the value three then in attempt has previously beenmade to transmit data on the subchannel C3 and that attempt was rejectedby the terminal interface unit because the channel did not correspond tothe channel then being used for data transmission.

If COSTAT is equal to three, control passes to conditional branch point1495, otherwise it passes to conditional branch point 1497. If COSTATwas equal to three then it is presumed that there is no point inrepeating the attempt to send data to the terminal interface unit unlessthe subchannel selected for data output from the terminal interface unitis part of the same channel that contains C3. Since the address of thedescriptor for the subchannel selected for data output from the terminalinterface unit is contained in the field RSELCH of the TIU descriptoraddressed by T3, and since the subchannel descriptor for the twosubchannels is one channel are sixteen words apart, the test shown inconditional branch point 1495 will transfer control to conditionalbranch point 1497 if the appropriate channel is not selected for dataoutput from the TIU and will otherwise pass control to block 1496. Block1496 enables a retry at burst transmission on subchannel C3 to TIU T3 bysetting the value two in field COSTAT of the subchannel descriptoraddressed by C3. Having done that control passes to conditional branchpoint 1497 shown in FIG. 25E.

The sequence starting at conditional branch point 1497 makes certaintests to see whether a start of burst output transmission is justifiedon subchannel C3. First, conditional branch point 1497 checks whetherthe subchannel specified as being selected is in fact subchannel C3. Itdoes this by comparing the fields SSELCH in the TIU descriptor whoseaddress is T3 with the value of C3. If they are unequal control passesto the end of the routine at terminal indicator 1508.

Next, a test is made in block 1498 to insure that the housekeepingoperations are not performed while a data output transmission requestremains extant. That is indicated by the value 1 in the field COSTATbelonging to the channel descriptor addressed by C3. If the value 1 isfound, control is transferred to the end of the subroutine at terminalindicator 1508. Conditional branch point 1499 then checks to see whetherthe field COSTAT contains the value three, and, if so, transfers controlto the end of the subroutine at terminal indicator 1508.

The test shown in block 1500 is made in order to insure that bursttransmission to a terminal interface unit does not start until a certainspecified number of packets has been collected. That number is containedin the field MOUT to the subchannel descriptor. By comparing this fieldwith the field VOL, conditional branch point 1500 arranges to transfercontrol to block 1501 if either the requisite number of the packets havebeen collected or if among those packets that have been collected thereis one which signifies that it is the end-of-message. In any othercircumstance, control is transferred from conditional branch point 1500to the end of the subroutine at terminal indicator 1508.

The sequence starting in block 1501 initializes burst output. First, thevalue contained in the field MOUT in the subchannel descriptor pointedto by C3 is copied into the field AOUT of the type 2 descriptor pointedto by T3. Block 1502 then indicates that normal transmission is to takeplace by setting the value 0 in the field COSTAT belonging to thesubchannel descriptor addressed by C3.

Block 1503 is obeyed next. Its function is to send an SEL signal to theterminal interface unit indicating the channel on which subsequent datais to be transmitted. Block 1503 produces this effect by callingsubroutine REQSIG where the function code of one is in parameter F6.Block 1504 then sets the field SSTAT in the type 2 descriptor addressedby T3 equal to the value three, thereby indicating that the switchingunit must wait for an ACK signal from the terminal interface unit.Following that, in block 1505 the current time is stored in the fieldSTIME belonging to the type 2 descriptor whose address is in T3. Block1506 then calls the subroutine S.BUNDLE.OUT to perform the housekeepingassociated with bundle transmission on the subchannel addressed by C3 tothe TIU whose descriptor is addressed by T3. Block 1507 shows a call tosubroutine REQOUT whose effect is to place a request for attention bythe data output routine. That request will specify subchannel C3.Control then passes to the end of the subroutine at terminal indicator1508.

E.BURST.OUT SUBROUTINE OF THE CONTROL COMPUTER PROGRAM

FIG. 25F shows the subroutine E.BURST.OUT whose purpose is to performthe housekeeping associated with the end of an output burst. Thesubroutine requires two input parameters. Parameter C4 is the address ofthe subchannel descriptor, and parameter T4 is the address of itsassociated type 2 descriptor.

The subroutine begins at terminal indicator 1510. The first action takenis shown in conditional branch point 1511 where a test is made on thefield COSTAT in the subchannel descriptor addressed by C4. If that fieldcontains the value 1 then the subchannel has been queued for attentionby the data otuput routine and cannot at this time be processed for theend of burst transmission. In that case control passes from conditionalbranch point 1511 to the end of the subroutine at terminal indicator1516. Otherwise, control passes to block 1512. Block 1512 provisionallysets the field COSTAT in the subchannel descriptor addressed by C4 equalto the value two. That value indicates that future transmission isconditional upon the requisite amount of data being collected in thesubchannel addressed by C4. Conditional branch point 1513 then tests thefield TRCHAIN in the type 2 descriptor pointed to by T4 to determine ifit relates to a terminal interface unit or to a trunk. In the case thatit is a trunk, control passes from the control point 1513 to block 1515,otherwise control passes to block 1514. The field SSTAT in thedescriptor for a terminal interface unit contains the value two when theterminal interface unit has no burst transmission scheduled for it. Itis that status which is set by block 1514. Block 1515 is a call tosubrouine S.BURST.OUT which will make an attempt to start transmissionof another burst of data to a TIU. Finally, control passes to the end ofthe subroutine at terminal indicator 1516.

S.BUNDLE.OUT SUBROUTINE OF THE CONTROL COMPUTER PROGRAM

FIG. 25G shows the subroutine S.BUNDLE.OUT which handles thehousekeeping associated with the start of a new bundle for outputtransmission. The subroutine required one parameter, T5, which is theaddress of a type 2 descriptor.

The subroutine begins at terminal indicator 1520. The first action takenin this subroutine is to compute the maximum size that will be allowedfor the bundle to be sent to the TIU or trunk whose descriptor isaddressed by T5. That maximum is the smaller of the two valuescontained, respectively, in the fields A.OUT and N.OUT of the type 2descriptor. Block 1521 shows that this value is computed and stored inthe temporary location N5. Next to be obeyed is block 1522 wherein minusone times the value stored in temporary location N5 is inserted into thefield V.OUT contained in the type 2 descriptor pointed to by T5. Next,in block 1523, the value currently contained in the field A.OUT of thetype 2 descriptor addressed by T5 is reduced by the amount contained inthe storage location N5; after that, control passes to the end of thesubroutine at terminal indicator 1524.

REQSIG SUBROUTINE OF THE CONTROL COMPUTER PROGRAM

FIG. 25H shows the subroutine REQSIG whose function is to place arequest to the signal output routine for the transmission of a signal.That routine requires three parameters. T6 is the address of the type 2descriptor relating to the TIU or trunk to which the signal is to besent; F6 contains the function code for the signal to be sent; and H6contains, where appropriate, the value to be used in the CH field of thesignal.

The routine begins at terminal indicator 1530. The signal output routineoperates by taking entry from the circular queue pointed to by the fieldSXTAIL and SXHEAD in the type 1 descriptor. If these two fields areequal, then the queue is full and no further entry should be made.Conditional branch point 1531 compares the values in these two fieldsand if they are equal passes control to the end of the subroutine atterminal indictor 1537. Otherwise, control passes on to block 1532.Field SXTAIL in the type 1 descriptor whose address is contained in L isthe field which contains the address of the next queue entry to be usedfor the purpose of making requests for signal output. In block 1532 itis shown that this address is transferred to the temporary storagelocation B6. The ield FN in the queue entry addressed by B6 is set equalto the value contained in F6, then the CH field in the queue entryaddressed by B6 is set equal to the value contained in H6. Next, thefield TNML contained in the queue entry addressed by B6 is set equal tothe value contained in T6. These actions are carried out respectively byblocks 1533, 1534, and 1535. Finally, the queue pointers are updated bycopying into field SXTAIL in the type 1 descriptor whose address is in Lthe value of the next queue entry following the 1 addressed by B6. Theaddressed of that entry is contained in the field NEXT of the queueentry addressed by B6. After that action is taken, control passes to theend of the routine at terminal indicator 1537.

REQOUT SUBROUTINE OF THE CONTROL COMPUTER PROGRAM

FIG. 251 shows the subroutine REQOUT whose function is to requestattention by the data output routine. The single parameter of thissubroutine is C7, the address of a subchannel descriptor, being thesubchannel for which attention is required.

The subroutine begins at terminal indicator 1540. Conditional branchpoint 1541 tests the field COSTAT in the subchannel descriptor addressedby C7. Only if that field is 0 will an attempt be made to make an entryin the attention queue for the data output routine. In all other cases,conditional branch point 1541 transfers control to the end of theroutine at terminal indicator 1550. To signify that a queue entry hasbeen made field COSTAT is set equal to 1, as shown in block 1542. Thequeue entries themselves form a circular list in consecutive locationsthe first of which is pointed to by the field ATTNQ contained in thetype 1 descriptor. One entry in this list is processed each master frametime, that is once each 250 microseconds. It is therefore possible toestimate the delay before a particular service request will be honoredby computing the relative position of the queue entry in question andthe last queue entry processed by the data output routine. The positionof the latter is contained in the field DXLAST of the type 1 descriptor.

Since it is required to restrain the speed with which the switching unitsends data packets to a terminal interface unit, the subroutine REQOUTattempts to make a data output attention queue entry a specific distanceahead of the position indicated by the field DXLAST. The distance inquestion is stored as field RATE in the channel descriptor.

Resuming then the step-by-step description of the queuing action, block1543 initializes a counter in temporary location X7. Block 1544 thenputs in temporary location L7 the address of the type 1 descriptorassociated with channel C7. In block 1545 the position in the dataoutput attention queue of which it is required to make an entry iscomputed. That position is the sum of the values in the field RATE ofthe subchannel descriptor and the value in the field DXLAST in the type1 descriptor. This computation is performed modulo the length of thequeue which is contained in field DXLENGTH of the type 1 descriptorpointed to by L7. As shown in block 1545, the position of the queueentry is stored in temporary location B7. Conditional branch point 1546then shows that the current content of the specified queue entry isexamined and if it is 0 control passes to block l551 where thesubchannel address contained in C7 is copied into the queue entry. Ifthe queue entry is non-zero, then control passes to block 1547 for thepurpose of computing an alternative position into which to make thequeue entry. As is seen in block 1547, the alternative position iscomputed by adding one to the current position and doing this additionmodulo the length of the queue. The new position is stored in locationB7. Block 1548 shows that the contents of the temporary location X7 arethen increased by one and conditional branch point 1549 transferscontrol back to conditional branch point 1546 for another attempt atmaking a queue entry if the resulting value in X7 is less than 0. Theeffect of this action is to insure that only a limited number of queuingattempts are made. When X7 no longer contains a negative number, controlpasses from conditional branch point 1549 to the end of the routine atterminal indicator 1550.

ASSIGN.SPACE SUBROUTINE OF THE CONTROL COMPUTER PROGRAM

FIG. 25J shows subroutine ASSIGN.SPACE whose purpose is to obtain aspace assignment for the purposes of data input and storage. Theparameters required by that routine are C11, which is the address of asubchannel descriptor, and T11 which is the address of a type 2descriptor relating to that subchannel.

The routine begins at terminal indicator 15513. In block 1552 it is seenthat the temporary storage location V11 is set equal to the number whichis in the least significant eight bits of the field VOL in thesubchannel descriptor addressed by C11. The value so obtained is equalto the total number of data blocks currently queued for datatransmission with subchannel C11. The ASSIGN.SPACE subroutine willattempt to assign the number of storage locations equal to the numberstored in the field NIN of the subchannel descriptor addressed by T11.However, if, in making that assignment, the total number of blocksassigned to channel C11 will exceed the number stored in the field ALLOCof the subchannel C11, then the assignment will not take place and thedemand will be considered excessive at this time. Conditional branchpoint 1553 makes the necessary tests and transfers control to block 1559if the demand is excessive. Otherwise, control passes to conditionalbranch point 1554.

The storage location UNASSIGNED SPACE contains a value equal to thenumber of storage locations in the common pool available for assignment.Clearly if the space assignment is to be successful, that number of freestorage locations must not be less than the number which theASSIGN.SPACE subroutine wishes to assign to channel C11. Conditionalbranch point 1554 makes the necessary determination by comparing thevalue in the storage location UNASSIGNED SPACE with the value in thefield M.IN of the subchannel descriptor associated with C11. If thestorage assignment cannot be made, control is transferred to block 1559,otherwise control proceeds to block 1555. In order to record that theassignment has been made, the value stored in field M.IN of subchanneldescriptor C11 is transferred to field A.IN in the type 2 descriptorwhose address is contained in T11. That action is shown in block 1555.

In block 1556 it is seen that the value stored in the locationUNASSIGNED SPACE is reduced by the amount of the value contained in thefield M.IN of the subchannel descriptor addressed by C11. To indicatethat data transfer can now take place, a 0 is written into the fieldRSTAT of the type 2 descriptor addressed by T11 as is shown in block1557. Immediately thereafter, control passes to the end of thesubroutine at terminal indicator 1558. This subroutine is written toreturn to the calling routine in two different ways, one signifyingsuccess and the other signifying failure. When control reaches terminalindicator 1558 a success exit occurs

Referring now to block 1559, it was seen that control reached this pointif the space assignment could not in fact be made. To indicate this factthe value 1 is stored in the field RSTAT of the type 2 descriptoraddressed by T11. Control then passes to terminal indicator 1560 whichis the end of the subroutine and its fail exit to the calling routine.

RELEASE.SPACE SUBROUTINE OF THE CONTROL COMPUTER PROGRAM

FIG. 25K shows the subroutine RELEASE.SPACE whose function is to returnto the common pool a packet buffer which once was assigned and used forstoring data. The single input parameter to this subroutine is B12, theaddress of the packet buffer to be released.

The subroutine begins at terminal indicator 1565. In order to avoidtiming problems, the greater part of this routine is obeyed withinterrupts inhibited, as shown in blocks 1566 and 1569. After inhibitinginterrupts, control passes to block 1567 where the first step in placingthe packet buffer on the free space list is taken. The list of freepacket buffer starts in working store location FREESPACE. Block 1567shows that the address of the current head of the free storage list istransferred to the field NEXT of the packet buffer addressed by B12.Then block 1568 shows that the address contained in B12 is transferredto the storage location FREESPACE, thus placing the packet bufferaddressed by B12 on the free storage list. After allowing interrupts inblock 1569 the contents of the storage location UNASSIGNEDSPACE isincreased by 1 to indicate that there is now one more packet buffer inthe free list. That is shown in block 1570 which is the last before theend of the subroutine at terminal indicator 1571.

ASSIGN.TRUNK SUBROUTINE OF THE CONTROL COMPUTER PROGRAM

FIG. 25L shows at subroutine ASSIGN.TRUNK whose function is to obtain anidle trunk and assign it to a specified subchannel. The address of thedescriptor for the subchannel in question is the single parameter forthe subroutine and is denoted by C9.

The subroutine starts at terminal indicator 1575. When the subchannel C9is intended to transfer data on a trunk to another switching unit thenthe field SLOOP in the descriptor for that subchannel will contain theaddress of a descriptor for a transmission line and associated with thattransmission line will be a number of trunks each described by a singletype 2 descriptor. In block 1576 the address of the type 1 descriptor istransferred to temporary storage location L9. All those trunks, whichare not currently active and assigned to work for specific channels, arechained together and hang from the field TRLIST of the line descriptorL9. If that field in the line descriptor is 0, then no free trunk isavailable. Conditional branch point 1577 determines whether this is infact the case and, if there is no trunk available, transfers control tothe end of the subroutine at terminal indicator 1578. The subroutine hasin fact two ends and two styles of returning to the calling routine. Inone case the return signifies successful assignment of a trunk, in theother case the return signifies a failure to assign a trunk. Terminalindicator 1578 is the fail exit from subroutine ASSIGN.TRUNK.

Returning now to conditional branch point 1577, control will betransferred to block 1579 if the list of free trunks is not empty. In1579 it is shown that the address of the descriptor for the first ofthese trunks is copied into temporary storage location D9. The listwhich starts in field TRLIST passes through the fields TRCHAIN in thetrunk descriptors through all trunks that are free. Therefore, theassignment shown in block 1580 has the effect of removing one trunk fromthe list. In block 1580 the value contained in the field TRCHAIN of thetrunk addressed by D9 is copied into the field TRLIST of the linedescriptor addressed by L9. At this point D9 contains the address of thetrunk descriptor for the trunk that is to be assigned to the channel C9.To complete the assignment the following actions are taken. The valuethree is stored in the field SSTAT of the trunk description addressed byD9, and in block 1582 0 is written into the field A.OUT and V.OUT ofthat trunk descriptor.

In block 1581 it is seen that the address of the subchannel, namely,that value which is contained in C9, is transferred into the fieldSSELCH of the trunk descriptor whose address is contained in D9. Next,in block 1582, the value two is stored in the field COSTAT found in thesubchannel descriptor whose address is contained in C9. The field SINKin the subchannel descriptor normally contains the address of the trunkassigned to serve that subchannel. So, in block 1583, the valuecontained in D9 is stored in the field SINK of the subchannel descriptoraddressed by C9. The channel number used in STRT signal is contained inthe field CHANNO of the subchannel descriptor and block 1584 it is seenthat this value is transferred to the field SELNO of the trunkdescriptor addressed by D9.

Having thus completed the assignment of a trunk to the subchannel C9, anSTRT signal is sent along the trunk to the switching unit of thereceiving end. To cause this to happen, a call is made to subroutineREQSIG with input parameter F6 equal to 1. The action taken by thatsubroutine has already been specified. After completion of the call,control passes to the successful exit of the subroutine at terminalindicator 1586.

RELEASE.TRUNK SUBROUTINE OF THE CONTROL COMPUTER PROGRAM

FIG. 25M shows the subroutine RELEASE TRUNK whose purpose is todisassociate a trunk from a particular channel and make that trunkavailable to all channels sharing the same transmission line. The inputparameters to this subroutine are T10, the address of the trunkdescriptor for the trunk to be released, and C10, the address of thechannel descriptor currently associated with the trunk.

The routine starts at terminal indicator 1590. When the subchannel C10is not being served by a trunk, the field SINK in the descriptor forthat subchannel must be set to 0. That action is taken in block 1591.Block 1592 sets in temporary storage location L10 the address of thedescriptor for the line over which transmissions from subchannel C10 aresent. The address of that line descriptor is found in field SLOOP of thesubchannel descriptor addressed by C10.

In order to make the trunk available for reassignment, it must be addedto the chain of free trunks which starts at the field TRLIST in the linedescriptor whose address is now contained in temporary location L10. Allthese trunks in that list are connected by the fields TRCHAIN in thetrunk descriptor. Thus block 1593 is seen to add the trunk whosedescriptor address is T10 to the list starting in TRLIST of the linedescriptor whose address is contained in L10.

Having thus released the trunk, block 1594 is obeyed wherein the valuefour is stored in the status field SSTAT of the trunk T10. Thisindicates that the trunk is now idle. Finally, an IDL signal must besent over that trunk to the switching unit of the receiving end. Thataction is shown in block 1595 where a call is made to subroutine REQSIGwith the input parameter F6 set equal to two. After completion of thatcall, control passes to the end of the subroutine at terminal indicator1596.

RETREAT SUBROUTINE OF THE CONTROL COMPUTER PROGRAM

FIG. 25N shows the subroutine RETREAT whose function is to backtrackover the queue of data waiting to be transmitted in association with aparticular subchannel. Input parameters to the subroutine are T8, theaddress of the type 2 descriptor for the TIU or trunk affected by thebacktrack operation, and S8, a sequence number which determines how farthe backtrack operation should go. In fact S8 is the sequence number ofthe last packet successfully transmitted and therefore the sequencenumber of the most recently transmitted packet that need not be involvedin the backtrack operation.

The subroutine starts in terminal indicator 1600. It is seen that inblock 1601 the temporary storage location C8 is set equal to the addressof the descriptor for the subchannel which the TIU or trunk T8 iscurrently serving. The field SSELCH of the type 2 descriptor addressedby T8 contains the address of the subchannel descriptor in question. Ifthat subchannel is currently queued for attention by the data outputroutine then the backtrack operation cannot be made. That determinationis made by conditional branch point 1602 which, if the backtrack cannottake place, transfers control to the end of the subroutine at terminalindicator 1621. Otherwise, control passes on to conditional branch point1603. The action required on backtrack depends on the type of packetmost recently transmitted to the TIU or trunk described by T8.

If the state as stored in the field SSTAT of the type 2 descriptorcontains value three then an SEL or STRT signal was transmitted and theswitching unit is waiting for an ACK signal from the TIU or trunk. Ifthat is the case, conditional branch point 1603 transfers control toblock 1616. Otherwise, control passes to conditional branch point 1604.If the field SSTAT contains the value two or the value four then the TIUor trunk T8 is no longer involved in data transfer and no backtrack ispossible. In this case, conditional branch point 1604 transfers controlto the end of the subroutine at terminal indicator 1621. Otherwise,control passes to block 1605.

The distance of backtrack is determined by the calculation shown inblock 1605. That distance is the difference between the value containedin field SSEQ of the type 2 descriptor addressed by T8 and the sequencenumber S8 supplied an input parameter to the RETREAT subroutine. Thedifference between these two numbers is computed modulo 64 since thesequence number is a six-bit quantity and that difference is stored inthe temporary location D8. If D8 is 0, then no backtrack is required andconditional branch point 1606 will transfer control to conditionalbranch point 1613. Otherwise, control passes to block 1607.

In block 1607 it is seen that the value stored in D8 is subtracted fromthe value contained in the field V.OUT of the type 2 descriptoraddressed by T8. Then, in block 1608 the sequence number S8 is stored inthe field SSEQ of the type 2 descriptor addressed by T8. The statusfield SSTAT of the type 2 descriptor addressed by T8 is set equal to 0in block 1609 and the field COSTAT of the channel descriptor addressedby C8 is set equal to 0 in block 1610. The program loop involving blocks1611, 1612, and 1615 provides the backtrack operation acrossuntransmitted data blocks. Control passes once around this loop for eachdata block across which backtrack must pass. Block 1611 subtracts onefrom D8 each time around the loop and conditional branch point 1612checks to see when D8 goes negative transferring control out of the loopto conditional branch point 1613 when that happens.

Thus it is seen that control passes around the loop exactly the numberof times that is contained in the temporary storage location D8 beforethe loop execution begins. Each time around the loop block 1615 isobeyed. That block shows how the pointer NEXTOUT contained in thechannel descriptor addressed by C8 is updated. That pointer points to ablock in the queue of data associated with the subchannel and the fieldPREV in each queue entry contains the address of the queue entry for thedata which would previously have been transmitted. Thus, to backtrackacross one block of data it is necessary to copy the contents of thefield PREV from the queue entry addressed by NEXTOUT into the fieldNEXTOUT.

Turning now to the action which takes place when control has passed outof the loop to conditional branch point 1613, it is seen that thatbranch point tests the input parameter W8. That parameter will benon-zero if the reason for obeying the RETREAT routine is that theterminal interface unit corresponding to T8 rejected transmissions onthe ground that they were on a channel not the same as the one on whichthe terminal interface unit was currently transmitting. If that were thecase, then control passes to block 1620, otherwise it moves on to block1614. In block 1614 is a call on the subroutine REQOUT whose purpose isto make an entry in the list requesting the attention of the data outputroutine. After completion of that call control passes to the end of thesubroutine at terminal indicator 1621.

Returning to conditional branch point 1603, it is recalled that controlpasses through there to block 1616 if the backtrack operation wasrequested when the switching unit was waiting for an acknowledgment fromthe SEL or STRT signal. The action taken here is, first, to transfer thesequence number contained in S8 to the field SSEQ of the type 2descriptor addressed by T8, then conditional branch point 1617 tests theinput parameter W8 to see if it is zero. If non-zero, it indicates thata channel-select was sent to a terminal interface unit and the terminalinterface unit rejected the channel-select on the ground that thechannel number did not correspond to the number of the channel on whichdata transmission was currently taking place. If that is the case,control will pass through conditional branch point 1617 to block 1619.Otherwise, it will pass to block 1618.

It is seen that block 1618 calls for a retransmission of the SEL or STRTsignal. That block shows a call to subroutine REQSIG whose purpose is tomake a queue entry for the signal output routine. After requestingtransmission of this signal control passes to the end of the subroutineat terminal indicator 1621. When block 1619 is obeyed, the field CSTATin the channel descriptor addressed by C8 is set equal to three. Theeffect that this has is to prevent that channel from being automaticallyselected again until the same channel is selected for data transmissionout of the terminal interface unit.

From block 1619 to block 1620 it is seen that the field SSTAT in thetype 2 descriptor addressed by T8 is set equal to two. The purpose hereis to indicate that there is no known subchannel which is in a positionto transmit data to the TIU or trunk described by T8. After setting thisstatus field control passes to the end of the subroutine at terminalindicator 1621. ##SPC1## ##SPC2## ##SPC3## ##SPC4##

What is claimed is:
 1. A data transmission system for .Iadd.supportingdata cells among .Iaddend.a plurality of digital devices, .Iadd.a datacall being comprised of randomly occurring bursts of data withintervening pauses, .Iaddend.comprising means for virtually allocatingtransmission paths upon request .Iadd.preparatory to establishing datacalls .Iaddend.from any of said digital devices to any other of saiddigital .[.device.]. .Iadd.devices by assigning to each call adescription of transmission resources to convey the data .Iaddend.andmeans for activating said virtually allocated transmission for.[.paths.]. .Iadd.path in accordance with the assigned description.Iaddend.only .[.when.]. .Iadd.upon determination that a .Iaddend.data.Iadd.burst of the call .Iaddend.is actually transmitted.
 2. A digitaldata transmission system .Iadd.for supporting data calls among aplurality of digital devices, a data call being comprised of randomlyoccurring bursts of data with intervening pauses .Iaddend.including aplurality of transmission loops, each including at least one digitaldevice, comprising:means for virtually allocating a transmission pathfrom a digital device in one loop to a digital device in another loopcomprising a plurality of asynchronous links .Iadd.by assigning to eachcall a description of the links in the path, .Iaddend.and means foractivating particular ones of said links .Iadd.in accordance with thepath description .Iaddend.only when .Iadd.a .Iaddend.data .Iadd.burst ofthe call .Iaddend.is actually available at said particular ones fortransmission.
 3. A data transmission system comprising:means forreceiving requests to virtually allocate communication paths; means forstoring descriptions of requested communication paths; and means forusing the stored descriptions to create the requested communicationpaths only when data is actually available for transmission.
 4. A datatransmission system comprising:means for receiving requests to establishcommunication paths; means for storing descriptions of requestedcommunication paths comprising a plurality of asynchronous links; andmeans for activating particular ones of the plurality of links only whendata is actually available at the particular ones for transmission.
 5. Asystem for providing data communication between a plurality of digitaldevices comprising:means for receiving requests for the use ofcommunication paths from each one of said plurality of digital devices;means for virtually allocating communication paths in response to saidrequests and prior to actual use of said paths; and means for actuallyconnecting said virtually allocated communication paths at the time datais actually transmitted.
 6. A digital data transmission systemcomprising:a first switching unit; a first digital device attached tosaid first switching unit; a second switching unit connected to saidfirst switching unit; a second digital device attached to said secondswitching unit; means for virtually allocating a first transmission pathbetween said first digital device and said first switching unit; meansfor virtually allocating a second transmission path between said firstswitching unit and said second switching unit; means for virtuallyallocating a third transmission path between said second switching unitand said second digital device; and means for selectively activatingeach of said first, second, and third virtually allocated transmissionpaths.
 7. The digital data transmission system of claim 6 wherein eachof the three means for virtually allocating a transmission path furthercomprises:means for storing parameters characterizing the data which isto be transmitted; and means for initiating the virtual allocation ofthe next succeeding transmission path.
 8. The digital data transmissionsystem of claim 6 wherein said means for selectively activating each ofsaid first, second, and third virtually allocated transmission pathsfurther comprises:means for activating said first virtually allocatedtransmission path only when said first digital device is actuallytransmitting data; means for activating said second virtually allocatedtransmission path only when said first switching unit is actuallyretransmitting data received from said first digital device; means foractivating said third virtually allocated transmission path only whensaid second switching unit is actually retransmitting that data receivedfrom said retransmission by said first switching unit.
 9. The digitaldata transmission system of claim 8 wherein each of the three means foractivating a transmission path further comprises:means for receivingincoming data which is to be retransmitted on said transmission path;means for storing said incoming data; and means for retransmitting saiddata on said transmission path.
 10. The digital data transmission systemof claim 9 wherein said means for storing said incoming data furthercomprises:means for selectively limiting the total amount of incomingdata which is stored at any time.
 11. The digital data transmissionsystem of claim 10 wherein said selectively limiting means furthercomprises:means for causing the device that is transmitting saidincoming data to cease transmission when the amount of said incomingdata that has not been retransmitted on said transmission path reaches aprespecified value.
 12. A system for transmitting data between digitaldevices comprising:a plurality of interconnected program-controlledswitching units; at least one program-controlled terminal interface unitattached to each one of said plurality of interconnectedprogram-controlled switching units for communication therewith by adigital device.
 13. The system of claim 12 further comprising:means forselectively limiting the amount of buffering that said system providesin each switching unit for each digital device that is attached thereto.14. The system of claim 13 further comprising:means for selectivelylimiting the minimum amount of data that said system permits eachdigital device attached thereto to transmit in a single burst oftransmission.
 15. The system of claim 14 further comprising:means forselectively limiting the minimum amount of data that said systemtransmits to each digital device attached thereto in a single burst oftransmission.
 16. The system of claim 14 further comprising:means forselectively limiting the rate at which said system permits each digitaldevice attached thereto to transmit data.
 17. The system of claim 15further comprising:means for selectively limiting the rate at which saidsystem transmits data to each digital device attached thereto.
 18. Themethod of transmitting data comprising the steps of:receiving requestsfor the use of transmission resources from transmitting devices; storingdescriptions of the transmission resources necessary to honor thereceived requests; committing transmission resources to particulartransmitting devices in accordance with the stored descriptions only atthe time data is actually transmitted. .Iadd.
 19. The method oftransmitting data in data calls comprised of randomly occurring burstsof data with intervening pauses, comprising the steps of: receivingrequests for the use of transmission resources from transmittingdevices; storing a description of the transmission resources necessaryto honor each received request; and committing transmission resources toparticular transmitting devices in accordance with the storeddescriptions only at a time when it is determined that a data burst isactually transmitted. .Iaddend.